Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Multiple-Valued Logic Synthesis and Optimization
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.ORCID iD: 0000-0001-7382-9408
2002 (English)In: Logic Synthesis and Verification / [ed] S. Hassoun and T. Sasao, Springer, 2002, 1st, 89-114 p.Chapter in book (Refereed)
Place, publisher, year, edition, pages
Springer, 2002, 1st. 89-114 p.
Series
The Springer International Series in Engineering and Computer Science
Keyword [en]
Multiple-Valued Logic, many-valued logic, multi-valued logic
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-165596DOI: 10.1007/978-1-4615-0817-5_4ISBN: 978-1-4613-5253-2 (print)OAI: oai:DiVA.org:kth-165596DiVA: diva2:808630
Note

NR 20150507

Available from: 2015-04-29 Created: 2015-04-29 Last updated: 2015-05-07Bibliographically approved

Open Access in DiVA

No full text

Other links

Publisher's full text

Authority records BETA

Dubrova, Elena

Search in DiVA

By author/editor
Dubrova, Elena
By organisation
Electronics and Embedded Systems
Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar

doi
isbn
urn-nbn

Altmetric score

doi
isbn
urn-nbn
Total: 731 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf