Large scale integration of graphene transistors for potential applications in the back end of the line
2015 (English)In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 108, 61-66 p.Article in journal (Refereed) Published
A chip to wafer scale, CMOS compatible method of graphene device fabrication has been established, which can be integrated into the back end of the line (BEOL) of conventional semiconductor process flows. In this paper, we present experimental results of graphene field effect transistors (GFETs) which were fabricated using this wafer scalable method. The carrier mobilities in these transistors reach up to several hundred cm(2) V-1 s(-1). Further, these devices exhibit current saturation regions similar to graphene devices fabricated using mechanical exfoliation. The overall performance of the GFETs can not yet compete with record values reported for devices based on mechanically exfoliated material. Nevertheless, this large scale approach is an important step towards reliability and variability studies as well as optimization of device aspects such as electrical contacts and dielectric interfaces with statistically relevant numbers of devices. It is also an important milestone towards introduting graphene into wafer scale process lines.
Place, publisher, year, edition, pages
2015. Vol. 108, 61-66 p.
Graphene, Transistor, Process integration, Wafer scale
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-166314DOI: 10.1016/j.sse.2014.12.014ISI: 000353004400012ScopusID: 2-s2.0-84925599928OAI: oai:DiVA.org:kth-166314DiVA: diva2:811428
FunderEU, European Research Council, 228229, 307311
QC 201505122015-05-122015-05-072016-06-10Bibliographically approved