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Methodical Validation and verification of FPGA-code: Master’s Thesis at ABB Robotics
KTH, School of Information and Communication Technology (ICT).
2015 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

Proper verification of FPGA-code requires knowledge, skills, tools and resources. ABB Robotics uses FPGA technology in their robot control system. The increasing complexity of their FPGA designs requires increasingly more advanced verification methods.

This provides an appropriate research on methodologies, languages and tools for more detailed evaluation based on ABB Robotics requirements and possibilities. The thesis demonstrates the chosen methods, languages and tools for verification of a FPGA-design by verification methods that are state of the art.

The verification environment such as functional verification, open source VHDL verification methodology (OSVVM), and universal verification methodology (UVM) were investigated in practical tests followed by an evaluation of advantages and disadvantages of the tests according the company requirements. This provides the verification teams with different test environments and presents available options for verification development and future work.

Place, publisher, year, edition, pages
2015. , 50 p.
TRITA-ICT-EX, 2015:3
URN: urn:nbn:se:kth:diva-167128OAI: diva2:813103
Available from: 2015-05-21 Created: 2015-05-21 Last updated: 2015-05-21Bibliographically approved

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