Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE credits
Raising the abstraction level, from Register Transfer Level (RTL) to Transaction Level
Model (TLM), accelerates the design and simulation speed for Application Specific
Integrated Circuit (ASIC) design in modern industry.
TLM can be used for reference model for RTL in verification process. TLM can also be
used in High Level Synthesis (HLS) as the original model for RTL implementation. With
the development of design automation tools for HLS by big Electronic Design Automation
(EDA) vendors in recent years, it is now possible to generate RTL code from TLM directly
by these fully automated industry commercial tools.
When it comes up to automated ASIC design, the functional consistency between TLM and
RTL is the top task of the verification. Several methodologies are developed or under
development in both industry and research area. Some automated verification tools may
help to greatly reduce the verification effort.
This thesis report has proposed a flow for verifying the functional equivalence between
TLM/SystemC/C code against its corresponding RTL code. The RTL code is the result of
automated HLS from TLM. One commercial tool based on sequential equivalence
checking (SEC) has been evaluated and its limitations have been assessed. The way to
overcome those limitations by complementary verification methods has been scrutinized.
2015. , 65 p.