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HiWA: A hierarchical Wireless Network-on-Chip architecture
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems. University of Turku (UTU), Finland .
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
2014 (English)In: Proceedings of the 2014 International Conference on High Performance Computing and Simulation, HPCS 2014, 2014, 499-505 p.Conference paper (Refereed)
Abstract [en]

Due to high latency and high power consumption in long hops between operational cores of NoCs, the performance of such architectures has been limited. In order to fill the gap between computing requirements and efficient communications, a new technology called Wireless Network-on-Chip (WNoC) has been emerged. Employing wireless communication links between cores, the new technology has reasonably increased the performance of NoC. However, wireless transceivers along with associated antenna impose considerable area and power overheads in WNoCs. Thus, in this paper, we introduce a hierarchical WNoC called Hierarchical Wireless-based Architecture (HiWA) to use the wireless resources optimally. In the proposed approach the network is divided into subnets where intra-subnet nodes communicate through wire links while inter-subnet communications are almost handled by single-hop wireless links. On top of that, we have also defined performance evaluation parameters. Simulation results show that the proposed architecture reduces average packet latency 16% and power consumption 14% in comparison with its conventional counterparts.

Place, publisher, year, edition, pages
2014. 499-505 p.
Keyword [en]
Architecture, Latency, Network-on-Chip, Power Consumption, System-on-Chip, Wireless Network-on-Chip, Application specific integrated circuits, Computer architecture, Distributed computer systems, Electric power utilization, Microprocessor chips, Network architecture, Servers, VLSI circuits, Wireless interconnects, Wireless networks, Wireless telecommunication systems, Average packet latencies, Efficient communications, Evaluation parameters, High power consumption, Proposed architectures, Wireless communication links, Wireless transceiver
National Category
Computer Systems
URN: urn:nbn:se:kth:diva-167617DOI: 10.1109/HPCSim.2014.6903726ISI: 000361141700064ScopusID: 2-s2.0-84908632090ISBN: 9781479953127OAI: diva2:813976
2014 International Conference on High Performance Computing and Simulation, HPCS 2014, 21 July 2014 - 25 July 2014

QC 20150525

Available from: 2015-05-25 Created: 2015-05-22 Last updated: 2015-10-16Bibliographically approved

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Daneshtalab, MasoudTenhunen, Hannu
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