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Characterization of bonding surface and electrical insulation properties of inter layer dielectrics for 3D monolithic integration
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0003-0568-0984
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0001-9690-2292
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0003-0333-376X
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2015 (English)In: EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, 2015, 165-168 p.Conference paper, Published paper (Refereed)
Abstract [en]

We investigate the bonding and electrical insulation properties of oxide layers for use in 3D monolithic integration via direct wafer bonding. Low surface roughness layers deposited on 100 mm Si wafers by atomic layer deposition (ALD) at 200 °C-350 °C, provide with adequate layer transfer bonding interfaces. Wafer scale IV measurements were performed to investigate the leakage current. We demonstrate that ALD oxide can function as a reliable bonding surface and also exhibit leakage current values below the nA range. Both properties are important pillars for a successful 3D monolithic integration.

Place, publisher, year, edition, pages
2015. 165-168 p.
Keyword [en]
3D integration, atomic layer deposition, current leakage, defects, Ge, GeOI, inter layer dielectrics, monolithic, strained Ge, wafer bonding, Deposition, Germanium, Integration, Leakage (fluid), Monolithic integrated circuits, Silicon wafers, Surface roughness, Three dimensional integrated circuits, 3-D integration, Inter-layer dielectrics, Strained-Ge
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-167390DOI: 10.1109/ULIS.2015.7063799ISI: 000380427400042Scopus ID: 2-s2.0-84926444085ISBN: 9781479969111 (print)OAI: oai:DiVA.org:kth-167390DiVA: diva2:815212
Conference
2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2015; Bologna; Italy; 26 January 2015 through 28 January 2015
Note

QC 20150529

Available from: 2015-05-29 Created: 2015-05-22 Last updated: 2016-09-02Bibliographically approved

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Garidis, KonstantinosJayakumar, GaneshDentoni Litta, EugenioHellström, Per-Erik

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Garidis, KonstantinosJayakumar, GaneshAsadollahi, AliDentoni Litta, EugenioHellström, Per-ErikÖstling, Mikael
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