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Revisiting central limit theorem: Accurate Gaussian random number generation in VLSI
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.ORCID iD: 0000-0003-0565-9376
KTH, School of Information and Communication Technology (ICT), Communication Systems, CoS, Radio Systems Laboratory (RS Lab).ORCID iD: 0000-0001-9697-9978
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2015 (English)In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 23, no 5, 842-855 p., 6834810Article in journal (Refereed) Published
Abstract [en]

Gaussian random numbers (GRNs) generated by central limit theorem (CLT) suffer from errors due to deviation from ideal Gaussian behavior for any finite number of additions. In this paper, we will show that it is possible to compensate the error in CLT, thereby correcting the resultant probability density function, particularly in the tail regions. We will provide a detailed mathematical analysis to quantify the error in CLT. This provides a design space with more than four degrees of freedom to build a variety of GRN generators (GRNGs). A framework utilizes this design space to generate customized hardware architectures. We will demonstrate designs of five different architectures of GRNGs, which vary in terms of consumed memory, logic slices, and multipliers on field-programmable gate array. Similarly, depending upon application, these architectures exhibit statistical accuracy from low (4 σ ) to extremely high (12 σ). A comparison with previously published designs clearly indicate advantages of this methodology in terms of both consumed hardware resources and accuracy. We will also provide synthesis results of same designs in application-specific integrated circuit using 65-nm standard cell library. Finally, we will highlight some shortcomings associated with such architectures followed by their remedies.

Place, publisher, year, edition, pages
2015. Vol. 23, no 5, 842-855 p., 6834810
Keyword [en]
Additive white Gaussian noise (AWGN), central limit theorem (CLT), Gaussian, normal, random number generator (RNG)., Application specific integrated circuits, Degrees of freedom (mechanics), Design, Field programmable gate arrays (FPGA), Gaussian distribution, Gaussian noise (electronic), Hardware, Integrated circuit design, Number theory, Probability density function, Random errors, White noise, Additive White Gaussian noise, Central Limit Theorem, Gaussians, Random number generators, Random number generation
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-167741DOI: 10.1109/TVLSI.2014.2322573ISI: 000355212000005Scopus ID: 2-s2.0-84928722530OAI: oai:DiVA.org:kth-167741DiVA: diva2:815613
Note

QC 20150601

Available from: 2015-06-01 Created: 2015-05-22 Last updated: 2017-12-04Bibliographically approved

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Hemani, AhmedSilmane, Ben

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Malik, Jamshaid SarwarHemani, AhmedSilmane, Ben
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Electronics and Embedded SystemsRadio Systems Laboratory (RS Lab)
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Electrical Engineering, Electronic Engineering, Information Engineering

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