Exploring NoC jitter effect on simulation of spiking neural networks
2014 (English)In: Proceedings of the 2014 International Conference on High Performance Computing and Simulation, HPCS 2014, 2014, 693-696 p.Conference paper (Refereed)
The major bottleneck in simulation of large-scale neural networks is the communication problem due to one-to-many neuron connectivity. Network-on-Chip concept has been proposed to address the problem. This work explores the drawback that is introduced by interconnection networks - a delay jitter. The preliminary experiment is held in the spiking neural network simulator introducing variable communicational delay to the simulation. The performance degradation is reported.
Place, publisher, year, edition, pages
2014. 693-696 p.
network-on-chip, self-organizing maps, spiking neural networks, Conformal mapping, Intelligent agents, Jitter, Self organizing maps, Servers, VLSI circuits, Communication problems, Delay jitters, Jitter effect, Performance degradation, Computer simulation
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-167963DOI: 10.1109/HPCSim.2014.6903756ISI: 000361141700094ScopusID: 2-s2.0-84908636749ISBN: 978-1-4799-5313-4OAI: oai:DiVA.org:kth-167963DiVA: diva2:817065
2014 International Conference on High Performance Computing and Simulation, HPCS 2014, 21 July 2014 through 25 July 2014
QC 201506042015-06-042015-05-222015-10-16Bibliographically approved