Towards stochastic delay bound analysis for network-on-chip
2015 (English)In: Proceedings - 2014 8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014, 2015, 64-71 p.Conference paper (Refereed)
We propose stochastic performance analysis in order to provide probabilistic quality-of-service guarantees in on-chip packet-switching networks. In contrast to deterministic analysis which gives per-flow absolute delay bound, stochastic analysis derives per-flow probabilistic delay bounding function, which can be used to avoid over-dimensioning network resources. Based on stochastic network calculus, we build a basic analytic model for an on-chip router, propose and exemplify a stochastic performance analysis flow. In experiments, we show the correctness and accuracy of our analysis, and exhibit its potential in enhancing network utilization with a relaxed delay requirement. Moreover, the benefits of such relaxation is demonstrated through a video playback application.
Place, publisher, year, edition, pages
2015. 64-71 p.
Calculations, Microprocessor chips, Network-on-chip, Quality of service, Routers, Stochastic models, Stochastic systems, Switching networks, VLSI circuits, Analytic modeling, Bounding functions, Deterministic analysis, Net work utilization, Performance analysis, Quality of service guarantees, Stochastic analysis, Stochastic network calculus, Quality control
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-168333DOI: 10.1109/NOCS.2014.7008763ScopusID: 2-s2.0-84922539507ISBN: 9781479953479OAI: oai:DiVA.org:kth-168333DiVA: diva2:818088
8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014, 17 September 2014 through 19 September 2014
QC 201506082015-06-082015-06-022015-06-08Bibliographically approved