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Energy Efficient 3D Hybrid Processor-Memory Architecture for the Dark Silicon Age
Iran University of Science and Technology.
Iran University of Science and Technology.
Iran University of Science and Technology.
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. University of Turku, Finland.
2015 (English)In: 10th International Symposium on Reconfigurable and Communication-centric Systems-on-Chip, IEEE Press, 2015, 7238085Conference paper (Refereed)
Abstract [en]

With increasing the number of cores on the Chip-Multiprocessors (CMPs) as a result of continuous technology scaling, more cache resources are needed to feed all the cores.Hence, in order to improve performance by reducing off-chip memory access, inevitably on-chip caches should be increased.In on-chip cache hierarchy, last level cache (LLCs) is the largest one consuming more energy compared with the other levels in many-core CMPs as leakage power within the LLC has become a significant contributor in the overall chip power budget in deep sub-micron as well as dark silicon era. In this paper, we focus on exploiting Non-Volatile Memory (NVM) which is a new type of memory with promising features in shared distributed LLCs to decrease the leakage power consumption and mitigating the dark silicon phenomenon. In our proposed strategy, we first calculate Average Memory Access Time (AMAT) of running applications on the CMP in each predetermined interval by collected systems memory traffic. Based on the monitored AMATs, we then adaptively reconfigure Hybrid distributed LLC by selecting the proper memory type (i.e., SRAM bank or STT-RAM bank) at runtime.

Experiment results on the PARSEC benchmarks show that the proposed method provides up to 55.22% (on average 39.3%) energy reduction and 35.33% on average energy-delay product (EDP) improvement with only 6% performance degradation compared to the conventional methods where single cache technology is used.

Place, publisher, year, edition, pages
IEEE Press, 2015. 7238085
Keyword [en]
Cache reconfiguration, 3D integrated circuit, Coremultiprocessors (CMPs), Non-volatile memory (NVM), Average memory access time (AMAT), Dark Silicon
National Category
Embedded Systems Computer Systems
URN: urn:nbn:se:kth:diva-168993DOI: 10.1109/ReCoSoC.2015.7238085ISI: 000380396200008ScopusID: 2-s2.0-84954162670ISBN: 978-146737942-7OAI: diva2:819127
IEEE International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC’15),July 2-3, 2015, Bremen, Germany

QC 20150623, QC 20160519

Available from: 2015-06-10 Created: 2015-06-10 Last updated: 2016-09-22Bibliographically approved

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