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A 101.4 GOPS/W Reconfigurable and Scalable Control-centric Embedded Processor for Domain-specific Applications
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.ORCID iD: 0000-0002-7589-9749
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.ORCID iD: 0000-0003-0061-3475
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
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2016 (English)In: Proceedings - IEEE International Symposium on Circuits and Systems, IEEE, 2016, 1746-1749 p.Conference paper, Published paper (Refereed)
Abstract [en]

Increasing the energy efficiency and performance while providing the customizability and scalability is vital for embedded processors adapting to domain-specific applications such as Internet of Things. In this paper, we proposed a reconfigurable and scalable control-centric architecture, and implemented the design consisting of two cores and an on-chip multi-mode router in 65 nm technology. The reconfigurability is enabled by the restructurable sequence mapping table (SMT) thus the reorganizable functional units. Owing to the integration of the multi-mode router, on-chip or inter-chip network for multi-/many-core computing can be composed for performance extension on demand even in the post-fabrication stage. Control-centric design simplifies the control logic, shrinks the non-functional units and orchestrates the operations to increase the hard are utilization and reduce the excessive data movement for high energy efficiency. As a result, the processor can both conduct general-purpose processing with 29% smaller code size and application-specific processing with over 10 times performance improvement when implementing AES by SMT. The dual-core processor consumes 19.7 μW/MHz with die size of 3.5 mm2. The achieved energy efficiency is 101.4GOPS/W.

Place, publisher, year, edition, pages
IEEE, 2016. 1746-1749 p.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:kth:diva-169547DOI: 10.1109/ISCAS.2016.7538905Scopus ID: 2-s2.0-84983396457ISBN: 978-147995340-0 (print)OAI: oai:DiVA.org:kth-169547DiVA: diva2:822109
Conference
IEEE International Symposium on Circuit and System (ISCAS)
Note

QC 20160613

Available from: 2015-06-16 Created: 2015-06-16 Last updated: 2016-12-15Bibliographically approved
In thesis
1. Ultra-low-power Design and Implementation of Application-specific Instruction-set Processors for Ubiquitous Sensing and Computing
Open this publication in new window or tab >>Ultra-low-power Design and Implementation of Application-specific Instruction-set Processors for Ubiquitous Sensing and Computing
2015 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The feature size of transistors keeps shrinking with the development of technology, which enables ubiquitous sensing and computing. However, with the break down of Dennard scaling caused by the difficulties for further lowering supply voltage, the power density increases significantly. The consequence is that, for a given power budget, the energy efficiency must be improved for hardware resources to maximize the performance. Application-specific integrated circuits (ASICs) obtain high energy efficiency at the cost of low flexibility for various applications, while general-purpose processors (GPPs) gain generality at the expense of efficiency.

To provide both high energy efficiency and flexibility, this dissertation explores the ultra-low-power design of application-specific instruction-set processors (ASIP) for ubiquitous sensing and computing. Two application scenarios, i.e. high-throughput compute-intensive processing for multimedia and low-throughput low-cost processing for Internet of Things (IoT) are implemented in the proposed ASIPs.

Multimedia stream processing for human-computer interaction is always featured with high data throughput. To design processors for networked multimedia streams, customizing application-specific accelerators controlled by the embedded processor is exploited. By abstracting the common features from multiple coding algorithms, video decoding accelerators are implemented for networked multi-standard multimedia stream processing. Fabricated in 0.13 $\mu$m CMOS technology, the processor running at 216 MHz is capable of decoding real-time high-definition video streams with power consumption of 414 mW.

When even higher throughput is required, such as in multi-view video coding applications, multiple customized processors will be connected with an on-chip network. Design problems are further studied for selecting the capability of single processors, the number of processors, the capacity of communication network, as well as the task assignment schemes.

In the IoT scenario, low processing throughput but high energy efficiency and adaptability are demanded for a wide spectrum of devices. In this case, a tile processor including a multi-mode router and dual cores is proposed and implemented. The multi-mode router supports both circuit and wormhole switching to facilitate inter-silicon extension for providing on-demand performance. The control-centric dual-core architecture uses control words to directly manipulate all hardware resources. Such a mechanism avoids introducing complex control logics, and the hardware utilization is increased. Programmable control words enable reconfigurability of the processor for supporting general-purpose ISAs, application-specific instructions and dedicated implementations. The idea of reducing global data transfer also increases the energy efficiency. Finally, a single tile processor together with network of bare dies and network of packaged chips has been demonstrated as the result. The processor implemented in 65 nm low leakage CMOS technology and achieves the energy efficiency of 101.4 GOPS/W for each core.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2015. xvi, 74 p.
Series
TRITA-ICT, ISSN 1653-6363 ; 15:11
National Category
Computer Systems
Identifiers
urn:nbn:se:kth:diva-174896 (URN)978-91-7595-692-3 (ISBN)
Public defence
2015-11-04, Sal B, Electrum 229, Kista, 10:00 (English)
Opponent
Supervisors
Funder
VINNOVA
Note

QC 20151009

Available from: 2015-10-09 Created: 2015-10-08 Last updated: 2015-10-09Bibliographically approved

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Publisher's full textScopushttp://iscas2016.org/http://www.epapers.org/iscas2016/ESR/paper_details.php?PHPSESSID=ng0dlfrqsjllp8b5tretcg5n46&paper_id=1097

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Ma, NingLu, Zhonghai

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