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The use of self-aligned Ti silicide in integrated Si technology
KTH, Superseded Departments, Electronic Systems Design.
1998 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

The performance and cost efficiency of integrated circuits(IC) are constantly improved by a miniaturization of theindividual device dimensions. As a consequence, the materialand electrical properties of conductors and contacts becomecritical, and fabrication technology development meets newchallenges from the continuous reduction of devicedimensions.

Thin film refractory metal silicides have been widely usedbecause of their great importance for industrial applicationsin very large scale integration (VLSI) complementarymetal-oxide semiconductor (CMOS) circuits. The use of silicidesallows the formation of low resistance source, gate and draincontacts which can significantly reduce the resistance of aCMOS gate and the source/drain series resistance compared tonon-silicided structures, and hence improves speedperformance.

Most of the silicide applications are realized using aSelf-ALIgned siliCIDE (SALICIDE) process based on titanium(Ti). Titanium silicide (TiSi2) is one of the most attractive materials among therefractory metal silicides due to its relatively hightemperature stability and low reported resistivity. Thesuccessful application of the Ti SALICIDE process has beenreported for most of the IC fabrication technologies. Atsub-micron dimensions the process window for the formation ofTiSi2is very small and rapid thermal processing (RTP)has been developed and successfully used in many applications.For deep sub-micron linewidths a new technique forenhancingTiSi2formation has to be used because the processwindow for ordinary RTP formation of silicide becomes toonarrow.

The implementation of the Ti SALICIDE technology in astandard Si technology was investigated. The study focused onsilicide formation in different ambient, etch selectivity,bridging and the Ti - SiO2interaction. Moreover, sheet resistance andcontact resistance measurements were made and yield statisticson fabricated devices were studied in order to fullycharacterize the Ti SALICIDE process. A new etch procedure forself-aligned Ti silicide was proposed. Developed technology wassuccessfully applied in the laboratory scale device fabricationprocesses.

The realization of sub-micron VLSI circuits operating atlower voltages suffers from the high resistance of dopedpolysilicon. Hence the Ti SALICIDE process is still one of themost important technologies to enhance circuit performance.Observed difficulties with the formation of the low resistiveC54 titanium silicide phase on sub-micron polysilicon linesoutlined and inspired further studies. A novel method toenhance TiSi2formation from Mo/Ti bilayer was investigated. Aone step Ti SALICIDE process to form TiSi2from Mo/Ti/TiN was proposed. Based on the recentliterature, novel silicide concepts to maintain fabrication ofshallow junctions under the silicide; e.g. elevatedsource/drain approach or selective deposition of TiSi2are described. Progress in these fields indicatesthat TiSi2is still one of the strongest candidates forapplications in a future deep sub-micron CMOS technology.

Key words:very large scale integration, VLSI,self-aligned silicide, SALICIDE, titanium silicide, TiSi2, silicidation, bridging, etch selectivity,sub-micron, Mo/Ti bilayer, TiSi2applications.

Place, publisher, year, edition, pages
Institutionen för elektronisk systemkonstruktion , 1998. , 72 p.
Trita-FTE, ISSN 0284-0545 ; 9804
URN: urn:nbn:se:kth:diva-2681ISBN: 91-7170-309-8OAI: diva2:8368
Public defence
NR 20140805Available from: 2000-01-01 Created: 2000-01-01Bibliographically approved

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