A Many-Core Hardware Acceleration Platform for Short Read Mapping Problem Using Distributed Memory Interface with 3D-stacked Architecture
2014 (English)In: 2014 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP (SOC)Article in journal (Refereed) Published
Next Generation Sequencing technologies produce huge amounts of short reads consisting randomly fragmented DNA base pair strings, while assembling poses a challenge on the mapping of short reads to a reference genome in terms of both sensitivity and execution time. In this paper, we propose a many-core hardware acceleration platform for short read mapping based on hash-index method, which benefit from a distributed memory interface with 3D-stacked architecture for local memory access. Our design provides an amazingly 45012 times speedup over software approach for single end short reads and 21102 times for paired end reads, while also beats similar single FPGA solution for 1466 times in case of single end reads.
Place, publisher, year, edition, pages
IEEE Press, 2014.
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-171032ISI: 000356507900024ISBN: 978-1-4799-6890-9OAI: oai:DiVA.org:kth-171032DiVA: diva2:841313
16th International Symposium on System-on-Chip (SoC), OCT 28-29, 2014, Tampere, FINLAND
QC 201507132015-07-132015-07-132015-07-13Bibliographically approved