Least Upper Delay Bound for VBR Flows in Networks-on-Chip with Virtual Channels
2015 (English)In: ACM Transactions on Design Automation of Electronic Systems, ISSN 1084-4309, Vol. 20, no 3, 35Article in journal (Refereed) Published
Real-time applications such as multimedia and gaming require stringent performance guarantees, usually enforced by a tight upper bound on the maximum end-to-end delay. For FIFO multiplexed on-chip packet switched networks we consider worst-case delay bounds for Variable Bit-Rate (VBR) flows with aggregate scheduling, which schedules multiple flows as an aggregate flow. VBR Flows are characterized by a maximum transfer size (L), peak rate (p), burstiness (sigma), and average sustainable rate (rho). Based on network calculus, we present and prove theorems to derive per-flow end-to-end Equivalent Service Curves (ESC), which are in turn used for computing Least Upper Delay Bounds (LUDBs) of individual flows. In a realistic case study we find that the end-to-end delay bound is up to 46.9% more accurate than the case without considering the traffic peak behavior. Likewise, results also show similar improvements for synthetic traffic patterns. The proposed methodology is implemented in C++ and has low run-time complexity, enabling quick evaluation for large and complex SoCs.
Place, publisher, year, edition, pages
2015. Vol. 20, no 3, 35
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-171301DOI: 10.1145/2733374ISI: 000357174900002ScopusID: 2-s2.0-84934761719OAI: oai:DiVA.org:kth-171301DiVA: diva2:843231
QC 201507282015-07-282015-07-272015-07-28Bibliographically approved