The wavelengths of interest in today's communication systemfront-ends are in the same order of magnitude as the availabledevices and circuit sizes. So the wave nature of theinformation can not be neglected. Concurrently, the urge formore compact solutions, higher performance and lower cost,pushes the degree of integration to such complexities that itcan simply not be handled by a uniform design platform (atleast until 1996), using "classical"-design approaches in apractical manner.Depending on the nature of the application,the focus on the object to be optimized, changes. Novel blockarchitectures, adapted to high speed operation, as well as newcircuit topologies and a comprehensive understanding of thesignal propagation through the devices and circuit arenecessary.In this work, a common design methodology was used torealize Very High Speed Integrated Circuits (VHSICs) of variouscharacteristics in a unified platform consisting ofcommercially available CAD-software.
The necessary routines for automatic extraction ofinterconnect parasitics were implemented in commercial IC-CADsoftware (Cadence DFWII). The implementation allows choice ofinterconnect-parasitics based on "pure-capacitive", "RC-" orthird order "LRC-" filter. DC-lines and HF-lines are recognizedand allowed to be treated differently. Eye-diagram simulationson CMOS and bipolar gates on Si and HBT gates on InP, emulatingMSI Very High Speed circuits, showed expected behaviour of theeffect of interconnect on signal integrity at high bitrates inCMOS-DCL and bipolar ECL/CML topologies.
The routines were used to implement novel high speedchannel-encoder/decoder circuits. The circuits are aimed forapplications in parallel fiber optical communication links toachieve true DC-coupled transmission. The circuits wereoperational up to 1.3 Gb/s realized in Si-bipolar technology.All the circuits were operation after the first processinground
A number of new circuit approaches were utilized inrealizing a chip-set in InP-HBT technology for 40 Gb/slightwave communication systems. On-wafer measurements havebeen performed to verify circuit operations. As far asavailable measurement capabilities showed, all circuits arefunctionally fulfilling specifications for 40 Gb/s operation atless than or equal to 3 volts supply voltage. During the designphase especially the influence of interconnects on signalintegrity was investigated using the implemented routines. Allthe circuits were operational after the first processing round.No redesign was necessary. In addition to the above chip-set,an asynchronous 2 X 2 crosspoint switch in the same technologywas designed fabricated and characterized for an electronicsdemonstrator of the link and WDM applications. BER-measurementsat 20 Gb/s show no erroneous transmission. The eye-diagram at25 Gb/s was clearly open. Smallsignal transmissionmeasurements, show potential for 40 Gb/s operation already at2V supply voltage.
Finally the first analysis on two unpublished work ispresented. One on all-transistor high frequency bipolaroscillator with wide tuning range and the other on analysis ofdata regeneration part of a very high speed (>10 Gb/s)bitrate transparent 3R repeater.
Institutionen för elektronisk systemkonstruktion , 1998. , xi, 85 p.