Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Efficient STDP Micro-Architecture for Silicon Spiking Neural Networks
University of Turku, Finland.
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems. University of Turku, Finland.ORCID iD: 0000-0001-6289-1521
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. University of Turku, Finland.
Ecole Polytechnique Montreal, Canada.
Show others and affiliations
2014 (English)In: 2014 17TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD), 2014, 496-503 p.Conference paper, Published paper (Refereed)
Abstract [en]

Spiking neural networks (SNNs) are the closest approach to biological neurons in comparison with conventional artificial neural networks (ANN). SNNs are composed of neurons and synapses which are interconnected with a complex pattern. As communication in such massively parallel computational systems is getting critical, the network-on-chip (NoC) becomes a promising solution to provide a scalable and robust interconnection fabric. However, using NoC for large-scale SNNs arises a trade-off between scalability, throughput, neuron/router ratio (cluster size), and area overhead. In this paper, we tackle the trade-off using a clustering approach and try to optimize the synaptic resource utilization. An optimal cluster size can provide the lowest area overhead and power consumption. For the learning purposes, a phenomenon known as spike-timing-dependent plasticity (STDP) is utilized. The micro-architectures of the network, clusters, and the computational neurons are also described. The presented approach suggests a promising solution of integrating NoCs and STDP-based SNNs for the optimal performance based on the underlying application.

Place, publisher, year, edition, pages
2014. 496-503 p.
Keyword [en]
Spiking Neural Network, Networks-on-Chip, STDP, Neuron Clustering
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-172645DOI: 10.1109/DSD.2014.109ISI: 000358409000065Scopus ID: 2-s2.0-84928783203ISBN: 978-1-4799-5793-4 (print)OAI: oai:DiVA.org:kth-172645DiVA: diva2:849094
Conference
17th Euromicro Conference on Digital System Design (DSD), AUG 27-29, 2014, Verona, ITALY
Note

QC 20150827

Available from: 2015-08-27 Created: 2015-08-27 Last updated: 2016-04-13Bibliographically approved

Open Access in DiVA

No full text

Other links

Publisher's full textScopus

Authority records BETA

Daneshtalab, Masoud

Search in DiVA

By author/editor
Daneshtalab, MasoudEbrahimi, MasoumehTenhunen, Hannu
By organisation
Electronics and Embedded SystemsIndustrial and Medical Electronics
Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar

doi
isbn
urn-nbn

Altmetric score

doi
isbn
urn-nbn
Total: 36 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf