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Three-Dimensional Design Space Exploration for System Level Synthesis
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.ORCID iD: 0000-0002-4157-4487
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.ORCID iD: 0000-0003-0565-9376
2014 (English)In: 2014 17TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD), 2014, 419-426 p.Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, we propose an efficient and effective three-dimensional design space exploration method for mapping a DSP system in synchronous data flow graph format onto an RTL or lower level hardware description using constraint programming. The three dimensions are 1) schedule level parallelism (The parallelism of the executions for one DSP function, fully parallel, semi-parallel or fully serial), 2) function level parallelism (how many function implementations are used to implement each of the DSP functions), and 3) arithmetic level parallelism (how the function implementations are implemented). The design space exploration problem is formulated as a constraints satisfaction optimization problem and solved by the constraint programming solver in Google's or-tools. The proposed method is compared against two state-of-the-art commercial HLS tools for four realistic examples and one synthetic example. The metrics compared are runtime, accuracy and quality of results in terms of resource usage. We show on average, the proposed method is 85.22% faster compared to HLS tools, 4.3% more accurate and 8.27% better in quality of results. For the latter we have conservatively assumed the same function execution parallelism.

Place, publisher, year, edition, pages
2014. 419-426 p.
Keyword [en]
System Level Synthesis, Design Space Exploration, Constraint Programming
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-172644DOI: 10.1109/DSD.2014.45ISI: 000358409000055Scopus ID: 2-s2.0-84928822237ISBN: 978-1-4799-5793-4 (print)OAI: oai:DiVA.org:kth-172644DiVA: diva2:849102
Conference
17th Euromicro Conference on Digital System Design (DSD), AUG 27-29, 2014, Verona, ITALY
Note

QC 20150827

Available from: 2015-08-27 Created: 2015-08-27 Last updated: 2015-08-27Bibliographically approved

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Li, ShuoHemani, Ahmed

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