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Designing 2D and 3D network-on-chip architectures
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
2014 (English)Book (Other academic)
Abstract [en]

This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliability. Case studies are used to illuminate new design methodologies.

Place, publisher, year, edition, pages
Springer New York , 2014. , 265 p.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-174754DOI: 10.1007/978-1-4614-4274-5Scopus ID: 2-s2.0-84929574081ISBN: 9781461442745 (print)ISBN: 978-146144273-8 OAI: oai:DiVA.org:kth-174754DiVA: diva2:859482
Note

QC 20151007

Available from: 2015-10-07 Created: 2015-10-07 Last updated: 2015-10-07Bibliographically approved

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CiteExportLink to record
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  • apa
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