Prefetching for the Kilo-Instruction Processor
Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
The large latency of memory accesses in modern computer systems is a key obstacle to achieving high processor utilization. Techniques to reduce or tolerate large memory latencies become essential for achieving high processor utilization. Prefetch is one of the most widely studied mechanisms at literature. This mechanism predicts the future effective addresses of loads to bring in advance their data to the upper and faster levels of the memory hierarchy. Another technique to alleviate the memory gap is the out-of-order commit, implemented in the Kilo-Instruction processors. This technique is based on the fact that independent instructions of a delinquent load can be executed even if the data for that load is not still available. The goal of this thesis project is to study a stride prefetching mechanism built on top of a Kilo-Instruction processor. I implemented the stride prefetching mechanism on SimpleScalar 3.0 and evaluate several sets of prefetch parameters by simulating them in a Kilo-instruction processor environment using the SPEC2000 benchmarks. The results show that the prefetching scheme effectively eliminates a major portion of data access penalty for a uniprocessor environment but provides less than 15% speedup improvement when applied to the Kilo-Instruction processor.
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IdentifiersURN: urn:nbn:se:kth:diva-174843OAI: oai:DiVA.org:kth-174843DiVA: diva2:859497