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Chip-Package co design of high performance mixer for 5GHz WLAN with integrated passive components
KTH, School of Information and Communication Technology (ICT).
2015 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

A passive mixer is designed in a silicon germine process for use in a 5GHz WLAN receiver. The design is implemented as a fully on-chip design and copackage design with passive components integrated on the substrate in the package. Also for each implementation the performance is evaluated with twelve different bonding inductances, from 50pH to 2nH. To estimate connection parasitic floorplans have been made for normal wirebonding and solderbumps for each of the implementation. The performance parameters compared are conversion gain, noise close to signal, noise with high frequency offset to the signal and IIP3. Some performance differences can be found between different implementations but neither of the implementations can be consider superior to the other.

Place, publisher, year, edition, pages
2015.
Series
TRITA-ICT-EX, 2015:40
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-174899OAI: oai:DiVA.org:kth-174899DiVA: diva2:859813
Examiners
Available from: 2015-10-08 Created: 2015-10-08 Last updated: 2017-06-13Bibliographically approved

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e6e196ba021ff80401538a4e17489903f1984a3a4375220b94a866ae5d2ba320487ef3d58e96a17300530c312694fe03ad870cf445d34c724c5c2f6c51a7a659
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Electrical Engineering, Electronic Engineering, Information Engineering

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CiteExportLink to record
Permanent link

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Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf