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Design and Implementation of QoS Packet Scheduling Policies in Hardware
KTH, School of Information and Communication Technology (ICT).
2015 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

Network-on-Chip (NoC) is becoming de facto main stream interconnect scheme for today’s and future high performance low power CMPs and MPSoCs. One key challenge is still on predictable Quality-of-Service (QoS), which provides guaranteed delay and bandwidth under dynamic network contention. This thesis implements in Register Transfer Level (RTL) level using VHDL three different scheduling algorithms: WRR (Weighted Round Robin), WFQ (Weighted Fair Queuing) and SCFQ (Self Clock Fair Queueing). The unique design pioneers high flexibility by supporting generic number of flows. The thesis covers theories’ review, design description, simulations and performance analysis. It is synthesised using Synopsys on 40 nm low power technology maintaining promising performance. Finally, analysis of maximum frequency, worst case average delay and normalized fairness index is covered highlighting predictable worse case performance which is with high importance for a wide range of applications.

Place, publisher, year, edition, pages
2015.
Series
TRITA-ICT-EX, 2015:57
Keyword [en]
Packet scheduling, WRR, WFQ, SCFQ, Fairness, VHDL
Identifiers
URN: urn:nbn:se:kth:diva-175369OAI: oai:DiVA.org:kth-175369DiVA: diva2:860580
Examiners
Available from: 2015-10-13 Created: 2015-10-13 Last updated: 2015-10-13Bibliographically approved

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CiteExportLink to record
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  • apa
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Output format
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