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Multi-Stage Network Processor for an Independent HVDC grids Supervisory Control
KTH, School of Electrical Engineering (EES), Industrial Information and Control Systems.
2015 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

This thesis presents a Multi-Stage Network Processor as part of independentsupervisory control in HVDC grid connecting AC areas.The proposed Network Processor finds the topology of the grid building the AdjacencyMatrix, identifies islands and assigns DC slack bus. The approach consists of twolevels: 1) process of DC substation topology locally and 2) the secondary process atHVDC grid central supervisory controller.At the substation level, the Local Processor determines the branch/bus model of thesubstation including the possible standalone HVDC converters using breakers’ status.Substation Matrix holds information regarding the model of the part of substationconnected to DC grid, while Standing Alone Matrix is created when the converter inthe substation is not connected to DC grid. The same analysis is performed on all thesubstations locally and then the Substation Matrixes are sent to the Central Processorat SCADA level.At central level, the processor creates the global Adjacency Matrix for the wholeHVDC grid.For the islands detection, the corresponding Laplacian Matrix is built from theAdjacency Matrix and a clustering method is used to analyze eigenvectors of theLaplacian Matrix.The proposed Network Processor has been successfully tested using a 7-terminalsHVDC grid model.Besides, an extended version of current algorithm has been studied for the integratedand, with some restriction, for the distributed HVDC supervisory control architecture. This master thesis project has been completely studied and developed at the departmentof Industrial Information and Control Systems at KTH - Royal Institute of Technologyin Stockholm.

Place, publisher, year, edition, pages
2015. , 120 p.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
URN: urn:nbn:se:kth:diva-175791OAI: diva2:862327
Available from: 2015-10-21 Created: 2015-10-21 Last updated: 2015-10-21Bibliographically approved

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