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Fabrication of Nanowires
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0001-6705-1660
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0002-5845-3032
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2014 (English)In: Beyond CMOS Nanodevices 1, Wiley Blackwell , 2014, 5-23 p.Chapter in book (Other academic)
Abstract [en]

Several fabrication processes of silicon nanowires have been developed in the research community. They can be divided into bottom-up or top-down approaches. This chapter describes top-down fabrication of silicon nanowires using electron beam lithography (EBL), which combined with optical lithography can be a viable approach if not too many silicon nanowires need to be patterned on a wafer. It also describes the sidewall transfer lithography (STL) technique using I-line stepper lithography to pattern a vast amount of silicon nanowires on a silicon wafer. In addition the chapter examines how bottom-up Si nanowires synthesized by vapor-liquid-solid (VLS)-chemical vapor deposition (CVD) can be assembled at low cost in an efficient way for further use as a sensing material. Among the solution-based assembly methods for the nanostructured network (nanonet) fabrication, the vacuum filtration method is highly simple, versatile, low cost and scalable to large areas.

Place, publisher, year, edition, pages
Wiley Blackwell , 2014. 5-23 p.
National Category
Materials Chemistry Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-174718DOI: 10.1002/9781118984772.ch1Scopus ID: 2-s2.0-84926399351ISBN: 9781118984772 (print)ISBN: 9781848216549 (print)OAI: oai:DiVA.org:kth-174718DiVA: diva2:867571
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QC 20151105

Available from: 2015-11-05 Created: 2015-10-07 Last updated: 2015-11-05Bibliographically approved

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Hellström, Per-Erik

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CiteExportLink to record
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  • apa
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  • Other locale
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