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Power management architecture in McNoC
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.ORCID iD: 0000-0003-0565-9376
2012 (English)In: Scalable Multi-core Architectures: Design Methodologies and Tools / [ed] Soudris, Dimitrios and Axel Jantsch, Springer Science+Business Media B.V., 2012, 55-80 p.Chapter in book (Other academic)
Abstract [en]

In this chapter we present the power management architecture of the McNoC platform. The power management architecture of McNoC offers distributed Dynamic Voltage Frequency Scaling (DVFS) and power down services to the platform at a fine level of granularity, allowing independent setting of frequency and supply voltage to all switch and resource nodes in the platform. The design style enables hierarchical physical design and solves the clock-domain-crossing problem with a solution based on rationally-related frequencies, which avoids the overhead associated with handshake. The architecture allows arbitrary power management regions to be defined and region-wide power management commands affecting all nodes in a region can be issued by the software layer that we call as Power Management Intelligence (PMINT).

Place, publisher, year, edition, pages
Springer Science+Business Media B.V., 2012. 55-80 p.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-176210DOI: 10.1007/978-1-4419-6778-7_3Scopus ID: 2-s2.0-84929563877ISBN: 9781441967787 (ISBN); 144196777X (ISBN); 9781441967770 (ISBN) OAI: oai:DiVA.org:kth-176210DiVA: diva2:867683
Note

QC 20151106

Available from: 2015-11-06 Created: 2015-11-02 Last updated: 2015-11-06Bibliographically approved

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Hemani, Ahmed

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