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Scalable multi-core architectures: Design methodologies and tools
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
2012 (English)Collection (editor) (Other academic)
Abstract [en]

As Moore's law continues to unfold, two important trends have recently emerged. First, the growth of chip capacity is translated into a corresponding increase of number of cores. Second, the parallelization of the computation and 3D integration technologies lead to distributed memory architectures. This book describes recent research that addresses urgent challenges in many-core architectures and application mapping. It addresses the architectural design of many core chips, memory and data management, power management, design and programming methodologies. It also describes how new techniques have been applied in various industrial case studies.

Place, publisher, year, edition, pages
Springer Science+Business Media B.V., 2012. 1-223 p.
Series
Scalable Multi-core Architectures: Design Methodologies and Tools
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-176211DOI: 10.1007/978-1-4419-6778-7Scopus ID: 2-s2.0-84949179381ISBN: 9781441967787 (print)ISBN: 9781441967770 (print)OAI: oai:DiVA.org:kth-176211DiVA: diva2:867710
Note

QC 20151106

Available from: 2015-11-06 Created: 2015-11-02 Last updated: 2015-11-06Bibliographically approved

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