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Optimal Emitter Cell Geometry in High Power 4H-SiC BJTs
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0002-7510-9639
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0001-8108-2631
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0002-5845-3032
2015 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 36, no 10, 1069-1072 p.Article in journal (Refereed) Published
Abstract [en]

Three 4H-SiC bipolar junction transistor designs with different emitter cell geometries (linear interdigitated fingers, square cell geometry, and hexagon cell geometry) are fabricated, analyzed, and compared with respect to current gain, ON-resistance (R-ON), current density (J(C)), and temperature performance for the first time. Emitter size effect and surface recombination are investigated. Due to a better utilization of the base area, optimal emitter cell geometry significantly increases the current density about 42% and reduces the ON-resistance about 21% at a given current gain, thus making the device more efficient for high-power and high-temperature applications.

Place, publisher, year, edition, pages
[Salemi, Arash; Elahipanah, Hossein; Zetterling, Carl-Mikael; Ostling, Mikael] KTH Royal Inst Technol, Sch Informat & Commun Technol, SE-16440 Kista, Sweden., 2015. Vol. 36, no 10, 1069-1072 p.
Keyword [en]
Power 4H-SiC BJTs, current density, current gain, ON-resistance, surface recombination
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-176349DOI: 10.1109/LED.2015.2470558ISI: 000362288700025Scopus ID: 2-s2.0-84961120580OAI: oai:DiVA.org:kth-176349DiVA: diva2:867880
Funder
Swedish Energy Agency
Note

QC 20151106

Available from: 2015-11-06 Created: 2015-11-03 Last updated: 2017-12-01Bibliographically approved
In thesis
1. Silicon Carbide Technology for High- and Ultra-High-Voltage Bipolar Junction Transistors and PiN Diodes
Open this publication in new window or tab >>Silicon Carbide Technology for High- and Ultra-High-Voltage Bipolar Junction Transistors and PiN Diodes
2017 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Silicon carbide (SiC) is an attractive material for high-voltage and high-temperature electronic applications owing to the wide bandgap, high critical electric field, and high thermal conductivity. High- and ultra-high-voltage silicon carbide bipolar devices, such as bipolar junction transistors (BJTs) and PiN diodes, have the advantage of a low ON-resistance due to conductivity modulation compared to unipolar devices. However, in order to be fully competitive with unipolar devices, it is important to further improve the off-state and on-state characteristics, such as breakdown voltage, leakage current, common-emitter current gain, switching, current density, and ON-resistance.

In order to achieve a high breakdown voltage with a low leakage current, an efficient and easy to fabricate junction edge protection or termination is needed. Among different proposed junction edge protections, a mesa design integrated with junction termination extensions (JTEs) is a powerful approach. In this work, implantation-free 4H-SiC BJTs in two classes of voltage, i.e., 6 kV-class and 15 kV-class with an efficient and optimized implantation-free junction termination (O-JTE) and multiple-shallow-trench junction termination extension (ST-JTE) are designed, fabricated and characterized. These terminations result in high termination efficiency of 92% and 93%, respectively.

The 6 kV-class BJTs shows a maximum current gain of β = 44. A comprehensive study on the geometrical design is done in order to improve the on-state performances. For the first time, new cell geometries (square and hexagon) are presented for the SiC BJTs. The results show a significant improvement of the on-state characteristics because of a better utilization of the base area. At a given current gain, new cell geometries show a 42% higher current density and 21% lower ON-resistance. The results of this study, including an optimized fabrication process, are utilized in the 15 kV-class BJTs where a record high current gain of β = 139 is achieved.

Ultra-high-voltage PiN diodes in two classes of voltage, i.e., 10+ kV using on-axis 4H-SiC and 15 kV-class off-axis 4H-SiC, are presented. O-JTE is utilized for 15 kV-class PiN diodes, while three steps ion-implantation are used to form the JTE in 10+ kV PiN diodes. Carbon implantation followed by high-temperature annealing is also performed for the 10+ kV PiN diodes in order to enhance the lifetime. Both type diodes depict conductivity modulation in the drift layer. No bipolar degradation is observed in 10+ kV PiN diodes.

Place, publisher, year, edition, pages
KTH Royal Institute of Technology, 2017. 126 p.
Series
TRITA-ICT, 2017:02
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Information and Communication Technology
Identifiers
urn:nbn:se:kth:diva-197913 (URN)978-91-7729-183-1 (ISBN)
Public defence
2017-01-20, Ka-Sal C (Sal Sven-Olof Öhrvik), KTH, Kistagången 16, Kista, 10:00 (English)
Opponent
Supervisors
Funder
StandUpSwedish Energy AgencySwedish Research Council
Note

QC 20161209

Available from: 2016-12-09 Created: 2016-12-09 Last updated: 2017-01-24Bibliographically approved
2. Design Optimization and Realization of 4H-SiC Bipolar Junction Transistors
Open this publication in new window or tab >>Design Optimization and Realization of 4H-SiC Bipolar Junction Transistors
2017 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

4H-SiC-based bipolar junction transistors (BJTs) are attractive devices for high-voltage and high-temperature operations due to their high current capability, low specific on-resistance, and process simplicity. To extend the potential of SiC BJTs to power electronic industrial applications, it is essential to realize high-efficient devices with high-current and low-loss by a reliable and wafer-scale fabrication process. In this thesis, we focus on the improvement of the 4H-SiC BJT performance, including the device optimization and process development.

To optimize the 4H-SiC BJT design, a comprehensive study in terms of cell geometries, device scaling, and device layout is performed. The hexagon-cell geometry shows 42% higher current density and 21% lower specific on-resistance at a given maximum current gain compared to the interdigitated finger design. Also, a layout design, called intertwined, is used for 100% usage of the conducting area. A higher current is achieved by saving the inactive portion of the conducting area. Different multi-step etched edge termination techniques with an efficiency of >92% are realized.

Regarding the process development, an improved surface passivation is used to reduce the surface recombination and improve the maximum current gain of 4H-SiC BJTs. Moreover, wafer-scale lift-off-free processes for the n- and p-Ohmic contact technologies to 4H-SiC are successfully developed. Both Ohmic metal technologies are based on a self-aligned Ni-silicide (Ni-SALICIDE) process.

Regarding the device characterization, a maximum current gain of 40, a specific on-resistance of 20 mΩ·cm2, and a maximum breakdown voltage of 5.85 kV for the 4H-SiC BJTs are measured. By employing the enhanced surface passivation, a maximum current gain of 139 and a specific on-resistance of 579 mΩ·cm2 at the current density of 89 A/cm2 for the 15-kV class BJTs are obtained. Moreover, low-voltage 4H-SiC lateral BJTs and Darlington pair with output current of 1−15 A for high-temperature operations up to 500 °C were fabricated.

This thesis focuses on the improvement of the 4H-SiC BJT performance in terms of the device optimization and process development for high-voltage and high-temperature applications. The epilayer design and the device structure and topology are optimized to realize high-efficient BJTs. Also, wafer-scale fabrication process steps are developed to enable realization of high-current devices for the real applications.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2017. 116 p.
Series
TRITA-ICT, 2017:14
Keyword
4H-SiC, BJT, high-voltage and ultra-high-voltage, high-temperature, self-aligned Ni-silicide (Ni-SALICIDE), lift-off-free, wafer-scale, current gain, Darlington
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering; Information and Communication Technology
Identifiers
urn:nbn:se:kth:diva-211659 (URN)978-91-7729-481-8 (ISBN)
Public defence
2017-09-01, Sal B, Electrum, Kungliga Tekniska Högskolan, Kistagången 16, Kista, 10:00 (English)
Opponent
Supervisors
Note

QC 20170810

Available from: 2017-08-10 Created: 2017-08-09 Last updated: 2017-08-10Bibliographically approved

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