Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE credits
Since most protocols use a limited set of basic functions to define the protocol, the feasibility of runtime reconfigurable network protocol processor is studied in this thesis for next generation of Ericsson’s EMCAs (Ericsson Multi Core Architecture).
For this purpose, common blocks between two protocols of 10G Ethernet and CPRI4.2 was implemented in RTL level. For block level reconfigurability, generic function blocks are implemented in SystemVerilog, tested in ModelSim and synthesized in Synopsys 28nm technology. To achieve system level reconfigurability, muxing structure is used for blocks communications with an enable controller function.
The results presented in this work, confirm that it is possible to implement a runtime reconfigurable protocol processor in RTL level.
This work was performed at Ericsson AB, Digital ASIC Group at Kista, Stockholm, Sweden during the time period of September 2013 to May 2014.
2014. , 59 p.