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High Level Synthesis Evaluation of Tools and Methodology
KTH, School of Information and Communication Technology (ICT).
2014 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

The advances in silicon technology, as well as competitive time to market, in the recent decade have forced the design tools and methodologies to progress towards higher levels of abstraction. Raising the level of abstraction shortens the design cycle via elimination of details in design specification. One such new methodology is High Level Synthesis (HLS). HLS tools accept the behavioral design in the abstract level as the input and generate the detailed Register Transfer Level (RTL) code.

In this thesis project, the HLS methodology is introduced in the design flow and its advantages are outlined. We then evaluate and compare three HLS tools developed by market leading vendors, namely, C-to-Silicon, CatapultC and Synphonycc. To compare the HLS tools, an HLS input is developed for one of the Ericsson’s designs and the generated RTL is compared with the hand-written RTL based on several performance criteria.

Thereof, we discuss the choice of the best tool so as to facilitate adoption of HLS in Ericsson’s design flow. At last, capability of the HLS tools in the synthesis of designs with pure control flow is investigated.

Place, publisher, year, edition, pages
2014. , 81 p.
TRITA-ICT-EX, 2014:133
National Category
Computer and Information Science
URN: urn:nbn:se:kth:diva-177362OAI: diva2:872464
Available from: 2015-12-01 Created: 2015-11-19 Last updated: 2015-12-01Bibliographically approved

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