Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE credits
As large uniprocessors are no longer scaling in performance, chip multiprocessors (CMP) become the mainstream to build high-performance computers. CMP chips integrate various components such as processing cores, L1 caches and L2 caches (some also contain L3 caches, for example, in the IBM Power7 multicore processor) together, and multiple CMP chips with external memory banks make up a CMP system. As buses (although long the mainstay of system interconnect) are unable to keep up with increasing performance requirements, network-on-chip (NoC) offers an attractive solution to this communication crisis and is becoming the pervasive interconnection network in CMPs.
In NoC based CMP systems, regulating traffic flows has been shown to be an effective means to improve communication performance and reduce buffer requirements. However, existing flow regulation policies such as the ones describe in  and  are all static. The parameters (δ,ρ) of the regulators are hard-coded during system configuration, where δ bounds the traffic burst and ρ the traffic rate. Although static flow regulator can be used as a design instrument for System-on-Chip (SoC) architects to control quality-of-service and achieve cost-effective communication, the drawbacks from its static property cancel the gains in some situations.
In this thesis, we design a fuzzy flow regulation mechanism for network-onchip based CMPs. Being different from static flow regulation policy, our system makes regulation decisions dynamically according to the state of interconnection network. We use fuzzy logic to mimic the behaviors of an expert that validly controls the admission of input flows, with the aim of making better use of on-chip resources and decreasing communication delays.
We implement and test our design under Multi-facet’s General Executiondriven Multiprocessor Simulator (GEMS), which creates a platform that is similar to real CMP environment. Hardware imitating models such as L1 caches, L2 caches and memory banks help us to test our design thoroughly and comprehensively.
The experiments are done with both closed-loop and open-loop methods. Comparisons have been made between our design and static regulation policy. The results show that our fuzzy flow regulation system can make good regulation policy with all the testing cases.
2014. , 71 p.