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Modeling of KTH UTBSOI MOSFET
KTH, School of Information and Communication Technology (ICT).
2014 (English)Independent thesis Basic level (professional degree), 10 credits / 15 HE creditsStudent thesis
Abstract [en]

Semiconductor devices such as transistors and integrated circuits are everywhere in our daily lives, it's one of the most important foundations of today's information society. Nanotechnology enables the production of lighter, faster and more efficient components and systems.

Manufacturing technology has improved considerably over the past 40 years, but in recent years, the bulk transistors have reaching the limits of Moore’s law as the size shrinking too few tens of nanometers. The main difficulties are to reduce the power consumption, improve the speed meanwhile maintain the low manufacturing cost.

This has given an opportunity for some emerging semiconductor technologies. One of the most promising approaches is implementation of new device architectures, such as FinFET and UTBSOI.

This bachelor thesis covers the basics of compact modeling of UTBSOI MOSFET, by using the BSIMSOI compact model and SPICE software Cadence to model the KTH Ultra-Thin-Body Silicon-on-Insulator (UTB-SOI) transistor.

The result of this paper shows the accuracy of BSIMSOI and can be used for future extraction work.

Abstract [sv]

Halvledarkomponenter såsom transistorer och integrerade kretsar finns överallt i vår vardag, det är en av de viktigaste grunderna för dagens informationssamhälle. Nanoteknik möjliggör produktion av lättare, snabbare och effektivare komponenter och system.

Tillverkningstekniken har förbättrats avsevärt under de senaste 40 åren, men på de senaste åren har de bulktillverkade transistorerna nått gränserna för Moores lag, när storleken krymper till några tiotal nanometer. De största svårigheterna är att minska energiförbrukningen, förbättra hastigheten samt bevara den låga tillverkningskostnaden.

Detta har gett möjlighet för att utvecklar ny halvledarteknik. En av de mest lovande metoderna är implementering av nya transitor arkitekturer, till exempel FinFET och UTBSOI.

Detta examensarbete omfattar grunderna i modellering av SOIMOSFET, med hjälp av BSIMSOI och SPICE programvara Cadence kan man modellera KTH transistor.

Resultatet av denna studie visar noggrannheten hos BSIMSOI och kan användas för framtida arbete inom ämnet.

Place, publisher, year, edition, pages
2014. , 56 p.
Series
TRITA-ICT-EX, 2014:174
National Category
Computer and Information Science
Identifiers
URN: urn:nbn:se:kth:diva-177444OAI: oai:DiVA.org:kth-177444DiVA: diva2:872774
Examiners
Available from: 2015-11-25 Created: 2015-11-20 Last updated: 2017-08-03Bibliographically approved

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Citation style
  • apa
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