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Optimization of a Compact I–V Model forGraphene FETs: Extending Parameter Scalability for Circuit Design Exploration
Technical University of Catalonia.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
University of Siegen.
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2015 (English)In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, no 11, 3870-3875 p.Article in journal (Refereed) Published
Abstract [en]

An optimization of the current-to-voltage transfer characteristic of a graphene FET (GFET) compact model, based on drift-diffusion carrier transport, is presented. The improved accuracy at Dirac point extends the model usability for GFETs when scaling parameters, such as voltage supply, gate length, oxide thickness, and mobility, for circuit design exploration. The model's accuracy is demonstrated through fitting to GFETs processed in-house. The model has been written in a standard behavioral language, and extensively run in an analog circuit simulator for designing basic circuits, such as inverters and cascode cells, demonstrating its robustness.

Place, publisher, year, edition, pages
IEEE Press, 2015. Vol. 62, no 11, 3870-3875 p.
Keyword [en]
Circuit design, compact model, graphene FET (GFET), parameter extraction
National Category
Nano Technology
Research subject
Electrical Engineering
URN: urn:nbn:se:kth:diva-177541DOI: 10.1109/TED.2015.2479036ISI: 000364242000063ScopusID: 2-s2.0-84946122079OAI: diva2:873197
EU, FP7, Seventh Framework Programme, 317839

QC 20151130

Available from: 2015-11-23 Created: 2015-11-23 Last updated: 2015-11-30Bibliographically approved

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