Design exploration of graphene-FET based ring-oscillator circuits: A test-bench for large-signal compact models
2015 (English)In: IEEE International Symposium on Circuits and Systems (ISCAS), IEEE Communications Society, 2015, 2716-2719 p.Conference paper (Refereed)
This paper presents a design-oriented characterization of ring-oscillator (RO) circuits based on complementary-inverters (INVs) implemented with graphene-FET (GFET) devices. A large-signal GFET compact model based on drift-diffusion transport is benchmarked at the circuit level against a second GFET compact model based on virtual source. Transient-based simulations of a 3-cell RO yield performance metrics in terms of operating frequency and voltage dynamic range. Against these metrics, a comprehensive design space exploration covering as input design variables parameters as GFET gate-oxide thickness tOX and channel-length L is presented. Methodologically, the work presents a general-purpose design framework, illustrated for ROs, which establishes a vertical circuit-device co-design environment. Its double-fold outcome is to provide guidelines both to bottom-up dimension and size the circuit, as well as top-down refine GFET device models and in turn GFET technology.
Place, publisher, year, edition, pages
IEEE Communications Society, 2015. 2716-2719 p.
, IEEE International Symposium on Circuits and Systems, ISSN 0271-4302
graphene, model, FET
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject Electrical Engineering
IdentifiersURN: urn:nbn:se:kth:diva-177549DOI: 10.1109/ISCAS.2015.7169247ISI: 000371471002262ScopusID: 2-s2.0-84946214853ISBN: 978-1-4799-8391-9OAI: oai:DiVA.org:kth-177549DiVA: diva2:873225
IEEE International Symposium on Circuits and Systems (ISCAS)
FunderEU, FP7, Seventh Framework Programme, 317839
QC 201512142015-11-232015-11-232016-04-25Bibliographically approved