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Full Wafer Graphene Devices
KTH, School of Information and Communication Technology (ICT).
2013 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

Graphene, a remarkable material has not only opened new doors for the CMOS world of ever increasing integration but also has fueled the scientific curiosity to create a new class of 2‐dimensional materials. Among the one-dimensional carbon nanotubes and 3-dimensional Bucky balls of 60 carbon atoms (C60), graphene surely was the missing link. This 2-dimensional flat land, not only changed the conventional 3-D attributes of electron gas but also past the barrier of equilibrium transport for Dirac fermions.

Traditional methods of fabricating any transistor involve photolithography using organic photoresists to deposit source, drain and gate electrodes. This approach seems logical in micro‐fabrication of FETs but photoresist application and subsequent cleaning unavoidably cause doping of the delicate monatomic graphene layer. In this project, stencil lithography, a contact less lithography technique is applied to build G-FETs to minimize unintentional doping of graphene.

This master thesis focuses on the fabrication of G-FETs on wafer-scale flexible substrates (Parylene) using large area CVD‐grown graphene. Experimental work on transfer of large area CVD‐grown graphene layer from transition metal substrate, in this case Copper, to desired substrate, and electrical behavior of top and bottom gated devices are reported.

Place, publisher, year, edition, pages
2013. , 39 p.
TRITA-ICT-EX, 2013:236
National Category
Computer and Information Science
URN: urn:nbn:se:kth:diva-177893OAI: diva2:874896
Available from: 2015-11-30 Created: 2015-11-30 Last updated: 2015-11-30Bibliographically approved

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