Reinforcement Learning Based Self-Optimization of Dynamic Fault-Tolerant Schemes in Performance-Aware RecoBlock SoCs
2015 (English)Report (Other academic)
Partial and run-time reconfiguration (RTR) technology has increased the range of opportunities and applications in the design of systems-on-chip (SoCs) based on Field-Programmable Gate Arrays (FPGAs). Nevertheless, RTR adds another complexity to the design process, particularly when embedded FPGAs have to deal with power and performance constraints uncertain environments. Embedded systems will need to make autonomous decisions, develop cognitive properties such as self-awareness and finally become self-adaptive to be deployed in the real world. Classico-line modeling and programming methods are inadequate to cope with unpredictable environments. Reinforcement learning (RL) methods have been successfully explored to solve these complex optimization problems mainly in workstation computers, yet they are rarely implemented in embedded systems. Disruptive integration technologies reaching atomic-scales will increase the probability of fabrication errors and the sensitivity to electromagnetic radiation that can generate single-event upsets (SEUs) in the configuration memory of FPGAs. Dynamic FT schemes are promising RTR hardware redundancy structures that improve dependability, but on the other hand, they increase memory system traffic. This article presents an FPGA-based SoC that is self-aware of its monitored hardware and utilizes an online RL method to self-optimize the decisions that maintain the desired system performance, particularly when triggering hardware acceleration and dynamic FT schemes on RTR IP-cores. Moreover, this article describes the main features of the RecoBlock SoC concept, overviews the RL theory, shows the Q-learning algorithm adapted for the dynamic fault-tolerance optimization problem, and presents its simulation in Matlab. Based on this investigation, the Q-learning algorithm will be implemented and verified in the RecoBlock SoC platform.
Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2015. , 30 p.
, TRITA-ICT/ECS, 15:27
cognitive hardware, partial and run-time reconfiguration, FPGA, autonomic computing, self-awareness, self-healing, machine learning, dynamic fault-tolerance, partial and run-time reconfiguration, complex adaptive systems, self-awareness, self-healing, machine learning, dynamic fault-tolerance, complex adaptive systems
Other Electrical Engineering, Electronic Engineering, Information Engineering Computer Systems Embedded Systems
IdentifiersURN: urn:nbn:se:kth:diva-177999ISRN: KTH/ICT/ECS/R-15-27-SEOAI: oai:DiVA.org:kth-177999DiVA: diva2:875463
QC 201512012015-12-012015-12-012015-12-01Bibliographically approved