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DyMeP: An Infrastructure to Support Dynamic Memory Binding for Runtime Mapping in CGRAs
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.ORCID iD: 0000-0003-0565-9376
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2015 (English)In: Proceedings of the IEEE International Conference on VLSI Design, IEEE conference proceedings, 2015, no February, 547-552 p.Conference paper (Refereed)
Abstract [en]

Coarse Grained Reconfigurable Architectures (CGRAs) are emerging as enabling platforms to meet the high performance demanded by modern applications. Commonly, CGRAs are composed of a computation layer (that performs computations) and a memory layer (that provides data and config ware to the computation layer). Tempted by higher platform utilization and reliability, recently proposed CGRA soffer dynamic application remapping (for the computation layer). Distributed scratch pad (compiler programmed) memories offer high data rates, predictability and low the power consumption (compared to caches). Therefore, the distributed scratchpad memories are emerging as preferred implementation alternative for the memory layer in recent CGRAs. However, the scratchpad memories are programmed at compile time, and do not support dynamic application remapping. The existing solutions that allow dynamic application remapping either rely on fat binaries (that significantly enhance configuration memory requirements) or consider a centralized memory. To extract the benefits of both runtime remapping and distributed scratchpad memories, we present a design framework called DyMeP. DyMeP relies on late binding and provides the architectural support to dynamically remap data in CGRAs. Compared to the state of the art, the proposed technique reduces the configuration memory requirements (needed by fat binary solutions) and supports distributed shared scratchpad memory. Synthesis/Simulation results reveal that DyMeP promises a significant (up to 60%) reduction in config ware size at the cost of negligible additional overheads (less then 1%).

Place, publisher, year, edition, pages
IEEE conference proceedings, 2015. no February, 547-552 p.
Keyword [en]
CGRA, circuit switched network on chip, Coarse Grained Reconfigurable Architecture, Dynamic Memory Binding, late binding, Network on Chip, NOC, relative addressing, Embedded systems, Memory architecture, Multiprocessing systems, Network architecture, Network-on-chip, Program compilers, Reconfigurable architectures, Servers, Switching circuits, VLSI circuits, Circuit-switched networks, Dynamic memory, Late bindings, Cache memory
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
URN: urn:nbn:se:kth:diva-176128DOI: 10.1109/VLSID.2015.98ScopusID: 2-s2.0-84938247521OAI: diva2:875913
28th International Conference on VLSI Design, VLSID 2015 - held concurrently with the 14th International Conference on Embedded Systems, 3 January 2015 through 7 January 2015

QC 20151202

Available from: 2015-12-02 Created: 2015-11-02 Last updated: 2015-12-02Bibliographically approved

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Jafri, Syed M. A.Hemani, AhmedTenhunen, Hannu
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