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Optimization of Assertion Placement in Time-Constrained Embedded Systems
Embedded Intelligent Solutions (EIS) By Semcon AB, Sweden.ORCID iD: 0000-0003-1768-6697
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2011 (English)Conference paper (Refereed)
Abstract [en]

We present an approach for optimization of assertion placement in time-constrained HW/SW modules for detection of errors due to transient and intermittent faults. During the design phases, these assertions have to be inserted into the executable code and, hence, will always be executed with the corresponding code branches. As the result, they can significantly increase execution time of a module, in particular, contributing to a much longer execution of the worst case, and cause deadline misses. Assertions have different characteristics such as tightness (or "local error coverage") and execution latency. Taking into account these properties can increase efficiency of assertion checks in time-constrained embedded HW/SW modules. We have developed a design optimization framework, which (1) identifies candidate locations for assertions, (2) associates a candidate assertion to each location, and (3) selects a set of assertions in terms of performance degradation and assertion tightness. Experimental results have shown the efficiency of the proposed techniques.

Place, publisher, year, edition, pages
IEEE , 2011. 171-176 p.
National Category
Mechanical Engineering
Identifiers
URN: urn:nbn:se:kth:diva-179482DOI: 10.1109/ETS.2011.35ISI: 000301771000029ScopusID: 2-s2.0-80051954237OAI: oai:DiVA.org:kth-179482DiVA: diva2:883467
Conference
European Test Symposium (ETS11), Trondheim, Norway.
Note

QC 20160120

Available from: 2015-12-17 Created: 2015-12-17 Last updated: 2016-01-20Bibliographically approved

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Izosimov, Viacheslav
Mechanical Engineering

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ReferencesLink to record
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