Hardware/Software Optimization of Error Detection Implementation for Real-Time Embedded Systems
2010 (English)Conference paper (Other academic)
This paper presents an approach to system-level optimization of error detection implementation in the context of fault-tolerant real-time distributed embedded systems used for safety-critical applica-tions. An application is modeled as a set of processes communicat-ing by messages. Processes are mapped on computation nodes connected to the communication infrastructure. To provide resil-iency against transient faults, efficient error detection and recovery techniques have to be employed. Our main focus in this paper is on the efficient implementation of the error detection mechanisms. We have developed techniques to optimize the hardware/software implementation of error detection, in order to minimize the global worst-case schedule length, while meeting the imposed hardware cost constraints and tolerating multiple transient faults. We present two design optimization algorithms which are able to find feasible solutions given a limited amount of resources: the first one assumes that, when implemented in hardware, error detection is deployed on static reconfigurable FPGAs, while the second one considers partial dynamic reconfiguration capabilities of the FPGAs.
Place, publisher, year, edition, pages
IdentifiersURN: urn:nbn:se:kth:diva-179483OAI: oai:DiVA.org:kth-179483DiVA: diva2:883470
Intl. Conf. on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2010), Scottsdale, AZ, USA.
QC 201601192015-12-172015-12-172016-01-19Bibliographically approved