Analysis and Optimization of Fault-Tolerant Embedded Systems with Hardened Processors
2009 (English)Conference paper (Refereed)
In this paper we propose an approach to the design optimization of fault-tolerant hard real-time embedded systems, which combines hardware and software fault tolerance techniques. We trade-off between selective hardening in hardware and process re-execution in software to provide the required levels of fault tolerance against transient faults with the lowest-possible system costs. We propose a system failure probability (SFP) analysis that connects the hardening level with the maximum number of re-executions in software. We present design optimization heuristics, to select the fault-tolerant architecture and decide process mapping such that the system cost is minimized, deadlines are satisfied, and the reliability requirements are fulfilled.
Place, publisher, year, edition, pages
2009. 682-687 p.
IdentifiersURN: urn:nbn:se:kth:diva-179485DOI: 10.1109/DATE.2009.5090752OAI: oai:DiVA.org:kth-179485DiVA: diva2:883482
Design Automation and Test in Europe (DATE 2009), Nice, France.
QC 201601202015-12-172015-12-172016-01-20Bibliographically approved