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Synthesis of Fault-Tolerant Embedded Systems
Dept. of Computer and Information Science, Linköping University, SE-581 83 Linköping, Sweden.ORCID iD: 0000-0003-1768-6697
2008 (English)In: Proceedings -Design, Automation and Test in Europe, DATE, 2008, 1117-1122 p.Conference paper (Refereed)
Abstract [en]

This work addresses the issue of design optimization for fault-tolerant hard real-time systems. In particular, our focus is on the handling of transient faults using both checkpointing with rollback recovery and active replication. Fault tolerant schedules are generated based on a conditional process graph representation. The formulated system synthesis approaches decide the assignment of fault-tolerance policies to processes, the optimal placement of checkpoints and the mapping of processes to processors, such that multiple transient faults are tolerated, transparency requirements are considered, and the timing constraints of the application are satisfied.

Place, publisher, year, edition, pages
2008. 1117-1122 p.
National Category
Mechanical Engineering
URN: urn:nbn:se:kth:diva-179557DOI: 10.1109/DATE.2008.4484825ScopusID: 2-s2.0-49849097900OAI: diva2:883506
Design, Automation, and Test in Europe (DATE 2008), Munich, Germany.

QC 20161020

Available from: 2015-12-17 Created: 2015-12-17 Last updated: 2016-01-20Bibliographically approved

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Izosimov, Viacheslav
Mechanical Engineering

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