A Constraint Logic Programming Framework for the Synthesis of Fault-Tolerant Schedules for Distributed Embedded Systems
2007 (English)Conference paper (Refereed)
We present a constraint logic programming (CLP) approach for synthesis of fault-tolerant hard real-time applications on. distributed heterogeneous architectures. We address time-triggered systems, where processes and messages are statically scheduled based on schedule tables. We use process re-execution for recovering from multiple transient faults. We propose three scheduling approaches, which each present a trade-off between schedule simplicity and performance, (i) full transparency, (it) slack sharing and (iii) conditional, and provide various degrees of transparency. We have developed a CLP framework that produces the fault-tolerant schedules, guaranteeing schedulability in the presence of transient faults. We show how the framework call be used to tackle design optimization problems. The proposed approach has been evaluated using extensive experiments.
Place, publisher, year, edition, pages
IEEE , 2007. 756-759 p.
IdentifiersURN: urn:nbn:se:kth:diva-179561DOI: 10.1109/EFTA.2007.4416850ISI: 000254117100105ScopusID: 2-s2.0-47849107113ISBN: 978-142440826-9OAI: oai:DiVA.org:kth-179561DiVA: diva2:883532
12th IEEE Conf. on Emerging Technologies and Factory Automation (ETFA), Work-In-Progress Section, Patras, Greece.
QC 201601222015-12-172015-12-172016-01-22Bibliographically approved