Design Optimization of Time- and Cost- Constrained Fault-Tolerant Distributed Embedded Systems
2005 (English)Conference paper (Other academic)
In this paper we present an approach to the design optimization of fault tolerant embedded systems for safety-critical applications. Processes are statically scheduled and communications are performed using the time-triggered protocol. We use process re-execution and replication for tolerating transient faults. Our design optimization approach decides the mapping of processes to processors and the assignment of fault-tolerant policies to processes such that transient faults are tolerated and the timing constraints of the application are satisfied. We present several heuristics which are able to find fault-tolerant implementations given a limited amount of resources. The developed algorithms are evaluated using extensive experiments, including a real-life example.
Place, publisher, year, edition, pages
2005. 864-869 p.
IdentifiersURN: urn:nbn:se:kth:diva-179568DOI: 10.1109/DATE.2005.116ISI: 000228086900169ScopusID: 2-s2.0-33646914393OAI: oai:DiVA.org:kth-179568DiVA: diva2:884283
Design Automation and Test in Europe Conference (DATE 2005), Munich, Germany.
QC 201601192015-12-172015-12-172016-01-19Bibliographically approved