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Low Power Analog Interface Circuits toward Software Defined Sensors
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. Fudan Univeristy, China.
2016 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Internet of Things is expanding to the areas such as healthcare, home management, industrial, agriculture, and becoming pervasive in our life, resulting in improved efficiency, accuracy and economic benefits. Smart sensors with embedded interfacing integrated circuits (ICs) are important enablers, hence, variety of smart sensors are required. However, each type of sensor requires specific interfacing chips, which divides the huge market of sensors’ interface chips into lots of niche markets, resulting in high develop cost and long time-to-market period for each type. Software defined sensor is regarded as a promising solution, which is expected to use a flexible interface platform to cover different sensors, deliver specificity through software programming, and integrate easily into the Internet of Things. In this work, research is carried out on the design and implementations of ultra low power analog interface circuits toward software defined sensors for healthcare services based on Internet of Things.

   This thesis first explores architectures and circuit techniques for energy-efficient and flexible analog to digital conversion. A time-spreading digital calibration, to calibrate the errors due to finite gain and capacitor mismatch in multi-bit/stage pipelined converters, is developed with short convergence time. The effectiveness of the proposed technique is demonstrated with intensive simulations. Two novel circuit level techniques, which can be combined with digital calibration techniques to further improve the energy efficiency of the converters, are also presented. One is the Common-Mode-Sensing-and-Input-Interchanging (CSII) operational-transconductance-amplifier (OTA) sharing technique to enable eliminating potential memory effects. The other is a workload-balanced multiplying digital-to-analog converter (MDAC) architecture to improve the settling efficiency of a high linear multi-bit stage. Two prototype converters have been designed and fabricated in 0.13 μm CMOS technology. The first one is a 14 bit 50 MS/s digital calibrated pipelined analog to digital converter that employs the workload-balanced MDAC architecture and time-spreading digital calibration technique to achieve improved power-linearity tradeoff. The second one is a 1.2 V 12 bit 5~45 MS/s speed and power-scalable ADC incorporating the CSII OTA-sharing technique, sample-and-hold-amplifier-free topology and adjustable current bias of the building blocks to minimize the power consumption. The detailed measurement results of both converters are reported and deliver the experimental verification of the proposed techniques.

    Secondly, this research investigates ultra-low-power analog front-end circuits providing programmability and being suitable for different types of sensors. A pulse-width- -modulation-based architecture with a folded reference is proposed and proven in a 0.18 μm technology to achieve high sensitivity and enlarged dynamic range when sensing the weak current signals. A 8-channel bio-electric sensing front-end, fabricated in a 0.35 μm CMOS technology is also presented that achieves an input impedance of 1 GΩ, input referred noise of 0.97 Vrms and common mode rejection ratio of 114 dB. With the programmable gain and cut-off frequency, the front-end can be configured to monitor for long-term a variety of bio-electric signals, such as electrooculogram (EOG), electromyogram (EMG), electroencephalogram (EEG) and electrocardiogram (ECG) signals. The proposed front-end is integrated with dry electrodes, a microprocessor and wireless link to build a battery powered E-patch for long-term and continuous monitoring. In-vivo test results with dry electrodes in the field trials of sitting, standing, walking and running slowly, show that the quality of ECG signal sensed by the E-patch satisfies the requirements for preventive cardiac care.

   Finally, a wireless multimodal bio-electric sensor system is presented. Enabled by a customized flexible mixed-signal system on chip (SoC), this bio-electric sensor system is able to be configured for ECG/EMG/EEG recording, bio-impedance sensing, weak current stimulation, and other promising functions with biofeedback. The customized SoC, fabricated in a 0.18 μm CMOS technology, integrates a tunable analog front-end, a 10 bit ADC, a 14 bit sigma-delta digital to current converter, a 12 bit digital to voltage converter, a digital accelerator for wavelet transformation and data compression, and a serial communication protocol. Measurement results indicate that the SoC could support the versatile bio-electric sensor to operate in various applications according to specific requirements.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2016. , xv, 135 p.
Series
TRITA-ICT, 2015:25
Keyword [en]
IoT, software defined sensor, SoC, bio-medical electronics, bio-electric sensor, E-patch, wearable sensor, wearable healthcare system, pervasive healthcare, CMOS, ADC, digital calibration, analog front-end, folded reference.
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
URN: urn:nbn:se:kth:diva-179671ISBN: 978-91-7595-779-1 (print)OAI: oai:DiVA.org:kth-179671DiVA: diva2:885568
Public defence
2016-01-21, Sal A, Electrum, Electrum 229, Kista, 13:30 (English)
Opponent
Supervisors
Note

QC 20151221

Available from: 2015-12-21 Created: 2015-12-18 Last updated: 2017-03-29Bibliographically approved
List of papers
1. A time-spreading calibration technique for multi-bit/stage pipeline ADCs
Open this publication in new window or tab >>A time-spreading calibration technique for multi-bit/stage pipeline ADCs
2009 (English)In: 2009 International SoC Design Conference, ISOCC 2009, 2009, 416-419 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper describes a robust and effective calibration algorithm for pipelined analog-to-digital converters, which compensates for large gain errors, without the requirement for a long startup time as required by the other dither-based algorithms presented in literature. The proposed technique, time-spreading self-calibration, operates the front-end sample-and-hold stage in half rate at startup and cancels out the strong input-interference by using subtractive correlation, achieves a quick convergence. When the sample-and-hold stage operates in full rate as normal, the algorithm works as a background dither-based scheme and enables to calibrate time-variant gain errors. Simulation results show that it only needs wake-up time of 3 × 10 5·T s to correct a 15-bit pipelined ADC in the presence of realistic capacitor mismatch and finite op-amp gain, where T s is the sampling period.

Keyword
Calibration algorithm, Calibration techniques, Capacitor mismatch, Full rate, Gain errors, Half-rate, Pipeline ADCs, Pipelined ADCs, Pipelined analog-to-digital converter, Sample-and-hold, Sampling period, Self calibration, Simulation result, Startup time, Time-spreading, Time-variant gains, Up time, Calibration, Errors, Multicarrier modulation, Programmable logic controllers, Analog to digital conversion
National Category
Communication Systems
Identifiers
urn:nbn:se:kth:diva-152388 (URN)10.1109/SOCDC.2009.5423867 (DOI)2-s2.0-77951430286 (Scopus ID)978-142445034-3 (ISBN)
Conference
2009 International SoC Design Conference, ISOCC 2009, 22 November 2009 through 24 November 2009, Busan, China
Note

QC 20141001

Available from: 2014-10-01 Created: 2014-09-26 Last updated: 2016-01-27Bibliographically approved
2. A 50MS/s 80dB SFDR digital calibrated pipelined ADC with workload-balanced MDAC
Open this publication in new window or tab >>A 50MS/s 80dB SFDR digital calibrated pipelined ADC with workload-balanced MDAC
2011 (English)In: IEEE Int. Conf. Electron Devices Solid-State Circuits, EDSSC, 2011Conference paper, Published paper (Refereed)
Abstract [en]

A workload-balanced multiplying digital-to-analog converter (WB-MDAC) is proposed to improve the settling efficiency of multi-bit pipeline stages, and demonstrated in a 14-bit 50-MS/s digital calibrated pipelined ADC. The presented ADC occupies an active area of 1.3 mm 2 in 0.13-μm 1P8M CMOS technology, including internal reference buffers. It dissipates 76mW from a 1.2-V supply, and achieves 64.4 dB SNDR and over 80 dB SFDR. 

Series
2011 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2011
Keyword
Active area, CMOS technology, Digital-to-analog converters, Multi-bits, Pipelined ADCs, Reference buffers, Analog to digital conversion, CMOS integrated circuits, Digital devices, Multiplying circuits, Solid state devices
National Category
Communication Systems
Identifiers
urn:nbn:se:kth:diva-150614 (URN)10.1109/EDSSC.2011.6117737 (DOI)2-s2.0-84856090865 (Scopus ID)9781457719974 (ISBN)
Conference
2011 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2011, 17 November 2011 through 18 November 2011, Tianjin
Note

QC 20140908

Available from: 2014-09-08 Created: 2014-09-08 Last updated: 2016-12-23Bibliographically approved
3. A highly linear 1.2 V 12bit 5-45 MS/s CMOS pipelined ADC with CM-sensing-and-input-interchanged OTA sharing
Open this publication in new window or tab >>A highly linear 1.2 V 12bit 5-45 MS/s CMOS pipelined ADC with CM-sensing-and-input-interchanged OTA sharing
2012 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 72, no 1, 237-241 p.Article in journal (Refereed) Published
Abstract [en]

A 1.2 V 12bit programmable pipelined ADC is presented and implemented in 0.13 mu m CMOS technology. A common-mode-sensing-and-input-interchanged OTA-sharing technique is proposed to address the non-resetting and successive-stage crosstalk issues in conventional OTA-sharing technique. Speed options of 5-45 MS/s are available with scalable power obtained by adjusting the bias currents for OTAs, comparators, and reference buffers, etc., or the global bias current. The measured signal-to-distortion-and-noise ratio is in range of 62.5-69.2 dB, and the peak spurious free dynamic range is 80.7 dB for all speed options, while the figure-of-merit is in the range of 0.26-0.49 pJ/conversion. The core area is 1.5 mm(2).

Keyword
Pipelined ADC, OTA sharing, CM-sensing-and-input-interchanged, Programmable
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-98709 (URN)10.1007/s10470-012-9829-4 (DOI)000304874300025 ()2-s2.0-84861891357 (Scopus ID)
Note

QC 20120703

Available from: 2012-07-04 Created: 2012-07-02 Last updated: 2017-12-07Bibliographically approved
4. High-sensitivity photodetection sensor front-end, detecting organophosphourous compounds for food safety
Open this publication in new window or tab >>High-sensitivity photodetection sensor front-end, detecting organophosphourous compounds for food safety
Show others...
2013 (English)In: Proceedings of the Custom Integrated Circuits Conference, San Jose, CA: IEEE Press, 2013Conference paper, Published paper (Refereed)
Abstract [en]

A high-sensitivity, high dynamic range photodetection sensor front-end is presented, suitable for low-cost hand-held food safety systems. This sensor front-end for detecting organophosphorus (OP) compounds incorporates an on-chip deep N-well photodetector, pulse width modulation (PWM), and a folded reference. Designed in a 0.18um process, measurement results show an input optical power dynamic range of 71dB, a sensitivity of 3.6nW/cm2 (0.77pA), and a power consumption of 14.5uW. OP compound detection experiments demonstrate a limit of detection (LOD) of 0.16u mol/L, comparable to that of a commercial spectrophotometer.

Place, publisher, year, edition, pages
San Jose, CA: IEEE Press, 2013
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-179695 (URN)10.1109/CICC.2013.6658511 (DOI)2-s2.0-84892634915 (Scopus ID)9781467361460 (ISBN)
Conference
35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013; San Jose, CA; United States; 22 September 2013
Note

QC 20151221

Available from: 2015-12-21 Created: 2015-12-21 Last updated: 2016-03-23Bibliographically approved
5. An 8-channel readout front-end for long-term sleep quality monitoring
Open this publication in new window or tab >>An 8-channel readout front-end for long-term sleep quality monitoring
2011 (English)In: 2011 IEEE Biomedical Circuits and Systems Conference, BioCAS 2011, San Diego, CA: IEEE Press, 2011, 385-388 p.Conference paper, Published paper (Refereed)
Abstract [en]

An 8-channel readout front-end (RFE) for long-term sleep quality monitoring is presented in this paper and features high common-mode rejection ratio (CMRR) and low input referred noise. Each channel is composed of an AC coupled instrumentation amplifier (IA) with chopping spike filter (CSF), a programmable gain amplifier (PGA), and a buffer, while the bias generator and non-overlapping clock are shared by all channels. The proposed circuit, built in standard 0.35 μ m CMOS technology, consumes 101 μ A from 2.7 V, while occupying 5 mm 2 of chip area. According to the simulation, the AC coupled IA's CMRR is 118 dB and input referred noise is merely 0.55 μ Vrms. Meanwhile, the RFE is digitally programmable for different applications.

Place, publisher, year, edition, pages
San Diego, CA: IEEE Press, 2011
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-179696 (URN)10.1109/BioCAS.2011.6107808 (DOI)2-s2.0-84862967928 (Scopus ID)9781457714696 (ISBN)
Conference
2011 IEEE Biomedical Circuits and Systems Conference, BioCAS 2011; San Diego, CA; United States
Note

QC 20151221

Available from: 2015-12-21 Created: 2015-12-21 Last updated: 2016-01-27Bibliographically approved
6. A wireless 8-channel ECG biopotential acquisition system for dry electrodes
Open this publication in new window or tab >>A wireless 8-channel ECG biopotential acquisition system for dry electrodes
Show others...
2012 (English)In: Proceedings of the 2012 IEEE International Symposium on Radio-Frequency Integration Technology, Singapore: IEEE Press, 2012, 140-142 p.Conference paper, Published paper (Refereed)
Abstract [en]

A wireless 8-channel biopotential acquisition system for capturing electrocardiogram (ECG) using dry electrodes is presented. The ECG system consists of copper electrodes, a micropowered 8-channel custom ASIC, and an off-the-shelf microprocessor and bluetooth radio. Each analog channel of the custom ECG front-end is composed of a chopper-modulated instrumentation amplifier (CMIA) with chopping spike filter (CSF), a programmable gain amplifier (PGA), and a output buffer. Implemented in standard a 0.35 μm CMOS technology, the ECG front-end consumes 101 μA from a 2.7 V supply, occupying 5 mm2 of chip area. Measurement results show an input impedance of 1 G Ω, an input-referred noise of 0.97 μVrms (0.5 ∼ 100 Hz), and a CMRR of 114 dB. Finally, a complete wireless 8-channel ECG monitoring system incorporating this analog front-end is demonstrated, showing successful recordings of a capture ECG waveform using a smart phone.

Place, publisher, year, edition, pages
Singapore: IEEE Press, 2012
Keyword
ECG, dry metal electrode, wireless, chopper modulation, instrumentation amplifier.
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-179697 (URN)10.1109/RFIT.2012.6401640 (DOI)2-s2.0-84873148627 (Scopus ID)9781467323048 (ISBN)
Conference
2012 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2012; Singapore; Singapore
Note

QC 20151221

Available from: 2015-12-21 Created: 2015-12-21 Last updated: 2015-12-21Bibliographically approved
7. Biofeedback neuromuscular electrical stimulation front-end for dysphagia treatment
Open this publication in new window or tab >>Biofeedback neuromuscular electrical stimulation front-end for dysphagia treatment
Show others...
2014 (English)In: IEEE 2014 Biomedical Circuits and Systems Conference, BioCAS 2014 - Proceedings, IEEE Press, 2014, 612-615 p.Conference paper, Published paper (Refereed)
Abstract [en]

A dedicated front-end for biofeedback neuromuscular electrical stimulation (NESM) system is proposed. For controllable dysphagia treatment, the integrated circuit (IC) provides a stimulator front-end with programmable stimulation parameters (2μA-1mA current amplitude, DC-2KHz frequency, and variable duty cycle) and an electromyogram/impedance (EMG/ETI) readout front-end with programmable gain and bandwidth (42-80dB, 0.1Hz-1.2KHz) for biofeedback. Area-efficient, low-power but high precision current controlling is achieved by inducing the sigma-delta modulator technique in the stimulation channel. The measured impedance and EMG signal are used to determine the stimulation parameters, enabling a closed loop optimized treatment. The proposed front-end is fabricated in a 0.18 μm standard CMOS process technology and dissipates a peak power of 2.3 mW at the supply voltage of 1.8 V. Measurement results on a live person are also provided to validate the system's effectiveness.

Place, publisher, year, edition, pages
IEEE Press, 2014
Series
Biomedical Circuits and Systems Conference, ISSN 2163-4025
Keyword
Biofeedback, EMG, Neuromuscular electrical stimulation, CMOS integrated circuits, Delta modulation, Delta sigma modulation, Electromyography, Modulators, Measured impedance, Programmable gain, Programmable stimulation, Sigma Delta modulator, Standard CMOS process, Stimulation parameters
National Category
Medical Engineering
Identifiers
urn:nbn:se:kth:diva-167590 (URN)10.1109/BioCAS.2014.6981800 (DOI)000366049300171 ()2-s2.0-84920513530 (Scopus ID)9781479923465 (ISBN)
Conference
10th IEEE Biomedical Circuits and Systems Conference, BioCAS 2014, 22 October 2014 through 24 October 2014
Note

QC 20150529

Available from: 2015-05-29 Created: 2015-05-22 Last updated: 2016-12-05Bibliographically approved

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  • harvard1
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