Automated Power and Latency Management in Heterogeneous 3D NoCs
2015 (English)Conference paper (Refereed)
Beside different core sizes in many-core Systems-on-Chip, the costand reliability issues of TSVs move 3D NoCs toward heterogonousdesigns. Such heterogeneity introduces design complexity and newchallenges for obtaining a high performance, low power, low area,and a reliable design. By taking all these factors into account, wepropose a design as a combination of Q-Learning and deflectionrouting in a heterogeneous 3D NoCs. This design enables therouting algorithm to dynamically adjust itself to the underlyingtraffic condition and topology arrangement at run time. Thereby,the network can reach its optimal performance and minimum powerconsumption shortly after a reconfiguration either because of anoccurred fault in the network or a traffic change.
Place, publisher, year, edition, pages
Association for Computing Machinery (ACM), 2015. 33-38 p.
q-routing, deflection routing, q-learning, irregular NoC
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-179689DOI: 10.1145/2835512.2835517ScopusID: 2-s2.0-84959292826ISBN: 978-1-4503-3963-6/15/12OAI: oai:DiVA.org:kth-179689DiVA: diva2:885736
Eighth International Workshop on Network on Chip Architectures (NoCArc), 5 December 2015
QC 201602262015-12-212015-12-212016-04-13Bibliographically approved