Change search
ReferencesLink to record
Permanent link

Direct link
Automated Power and Latency Management in Heterogeneous 3D NoCs
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. University of Turku, Finland.
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.ORCID iD: 0000-0001-6289-1521
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. University of Turku, Finland.
2015 (English)Conference paper (Refereed)
Abstract [en]

Beside different core sizes in many-core Systems-on-Chip, the costand reliability issues of TSVs move 3D NoCs toward heterogonousdesigns. Such heterogeneity introduces design complexity and newchallenges for obtaining a high performance, low power, low area,and a reliable design. By taking all these factors into account, wepropose a design as a combination of Q-Learning and deflectionrouting in a heterogeneous 3D NoCs. This design enables therouting algorithm to dynamically adjust itself to the underlyingtraffic condition and topology arrangement at run time. Thereby,the network can reach its optimal performance and minimum powerconsumption shortly after a reconfiguration either because of anoccurred fault in the network or a traffic change.

Place, publisher, year, edition, pages
Association for Computing Machinery (ACM), 2015. 33-38 p.
Keyword [en]
q-routing, deflection routing, q-learning, irregular NoC
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-179689DOI: 10.1145/2835512.2835517ScopusID: 2-s2.0-84959292826ISBN: 978-1-4503-3963-6/15/12OAI: oai:DiVA.org:kth-179689DiVA: diva2:885736
Conference
Eighth International Workshop on Network on Chip Architectures (NoCArc), 5 December 2015
Note

QC 20160226

Available from: 2015-12-21 Created: 2015-12-21 Last updated: 2016-04-13Bibliographically approved
In thesis
1. Exploring the Scalability and Performance of Networks-on-Chip with Deflection Routing in 3D Many-core Architecture
Open this publication in new window or tab >>Exploring the Scalability and Performance of Networks-on-Chip with Deflection Routing in 3D Many-core Architecture
2016 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Three-Dimensional (3D) integration of circuits based on die and wafer stacking using through-silicon-via is a critical technology in enabling "more-than-Moore", i.e. functional integration of devices beyond pure scaling ("more Moore"). In particular, the scaling from multi-core to many-core architecture is an excellent candidate for such integration. 3D systems design follows is a challenging and a complex design process involving integration of heterogeneous technologies. It is also expensive to prototype because the 3D industrial ecosystem is not yet complete and ready for low-cost mass production. Networks-on-Chip (NoCs) efficiently facilitates the communication of massively integrated cores on 3D many-core architecture. In this thesis scalability and performance issues of NoCs are explored in terms of architecture, organization and functionality of many-core systems.

First, we evaluate on-chip network performance in massively integrated many-core architecture when network size grows. We propose link and channel models to analyze the network traffic and hence the performance. We develop a NoC simulation framework to evaluate the performance of a deflection routing network as the architecture scales up to 1000 cores. We propose and perform comparative analysis of 3D processor-memory model configurations in scalable many-core architectures.

Second, we investigate how the deflection routing NoCs can be designed to maximize the benefit of the fast TSVs through clock pumping techniques. We propose multi-rate models for inter-layer communication. We quantify the performance benefit through cycle-accurate simulations for various configurations of 3D architectures.

Finally, the complexity of massively integrated many-core architecture by itself brings a multitude of design challenges such as high-cost of prototyping, increasing complexity of the technology, irregularity of the communication network, and lack of reliable simulation models. We formulate a zero-load average distance model that accurately predicts the performance of deflection routing networks in the absence of data flow by capturing the average distance of a packet with spatial and temporal probability distributions of traffic.

The thesis research goals are to explore the design space of vertical integration for many-core applications, and to provide solutions to 3D technology challenges through architectural innovations. We believe the research findings presented in the thesis work contribute in addressing few of the many challenges to the field of combined research in many-core architectural design and 3D integration technology.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2016. xviii, 80 p.
Series
, TRITA-ICT, 2015:29
Keyword
Alpha-model, Average distance, B-Model, NoC, Zero-load predictive model, deflection routing, q-routing
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-179694 (URN)978-91-7595-803-3 (ISBN)
Public defence
2016-01-20, Hall C, Electrum, Isafjordsgatan 26, 16440, Kista, 13:00 (English)
Opponent
Supervisors
Note

QC 20151221

Available from: 2015-12-21 Created: 2015-12-21 Last updated: 2015-12-21Bibliographically approved

Open Access in DiVA

No full text

Other links

Publisher's full textScopushttp://dl.acm.org/citation.cfm?doid=2835512.2835517

Search in DiVA

By author/editor
Weldezion, Awet YemaneEbrahimi, MasoumehDaneshtalab, MasoudTehnhunen, Hannu
By organisation
Industrial and Medical ElectronicsElectronics and Embedded Systems
Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

Altmetric score

Total: 58 hits
ReferencesLink to record
Permanent link

Direct link