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Exploring the Scalability and Performance of Networks-on-Chip with Deflection Routing in 3D Many-core Architecture
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
2016 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Three-Dimensional (3D) integration of circuits based on die and wafer stacking using through-silicon-via is a critical technology in enabling "more-than-Moore", i.e. functional integration of devices beyond pure scaling ("more Moore"). In particular, the scaling from multi-core to many-core architecture is an excellent candidate for such integration. 3D systems design follows is a challenging and a complex design process involving integration of heterogeneous technologies. It is also expensive to prototype because the 3D industrial ecosystem is not yet complete and ready for low-cost mass production. Networks-on-Chip (NoCs) efficiently facilitates the communication of massively integrated cores on 3D many-core architecture. In this thesis scalability and performance issues of NoCs are explored in terms of architecture, organization and functionality of many-core systems.

First, we evaluate on-chip network performance in massively integrated many-core architecture when network size grows. We propose link and channel models to analyze the network traffic and hence the performance. We develop a NoC simulation framework to evaluate the performance of a deflection routing network as the architecture scales up to 1000 cores. We propose and perform comparative analysis of 3D processor-memory model configurations in scalable many-core architectures.

Second, we investigate how the deflection routing NoCs can be designed to maximize the benefit of the fast TSVs through clock pumping techniques. We propose multi-rate models for inter-layer communication. We quantify the performance benefit through cycle-accurate simulations for various configurations of 3D architectures.

Finally, the complexity of massively integrated many-core architecture by itself brings a multitude of design challenges such as high-cost of prototyping, increasing complexity of the technology, irregularity of the communication network, and lack of reliable simulation models. We formulate a zero-load average distance model that accurately predicts the performance of deflection routing networks in the absence of data flow by capturing the average distance of a packet with spatial and temporal probability distributions of traffic.

The thesis research goals are to explore the design space of vertical integration for many-core applications, and to provide solutions to 3D technology challenges through architectural innovations. We believe the research findings presented in the thesis work contribute in addressing few of the many challenges to the field of combined research in many-core architectural design and 3D integration technology.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2016. , xviii, 80 p.
Series
TRITA-ICT, 2015:29
Keyword [en]
Alpha-model, Average distance, B-Model, NoC, Zero-load predictive model, deflection routing, q-routing
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-179694ISBN: 978-91-7595-803-3 (print)OAI: oai:DiVA.org:kth-179694DiVA: diva2:885738
Public defence
2016-01-20, Hall C, Electrum, Isafjordsgatan 26, 16440, Kista, 13:00 (English)
Opponent
Supervisors
Note

QC 20151221

Available from: 2015-12-21 Created: 2015-12-21 Last updated: 2015-12-21Bibliographically approved
List of papers
1. Zero-load Predictive Model for Performance Analysis in Deflection Routing NoCs
Open this publication in new window or tab >>Zero-load Predictive Model for Performance Analysis in Deflection Routing NoCs
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2015 (English)In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 39, no 8, 634-647 p.Article in journal (Refereed) Published
Abstract [en]

We study a static model for 2-D and 3-D networks that accurately represents the average distance travelled by packets under deflection routing, which is a specific form of adaptive routing. The model captures static properties of the network topology and the spatial distribution of traffic, but does not take into account traffic loading and congestion. Even though this static model cannot accurately predict packet latency under high load, we contend that it is a perfect predictor of deflection routing networks’ relative performance under any load condition below saturation, and thus always correctly predicts the optimum network configuration. This is verified through cycle-accurate simulations of congested and uncongested networks with fully adaptive, deflection routing for regular traffic patterns such as uniform random, localised, bursty, and others, as well as irregular patterns in both regular and irregular networks. As the networks with minimal average distance perform best even under high traffic load, the average distance model establishes a robust relation between a static network property, average distance, and network performance under load, providing new insight into network behaviour and an opportunity to identify the optimal network configuration without time-consuming simulations.

Place, publisher, year, edition, pages
Elsevier B.V.: , 2015
Keyword
Alpha-model, Average distance, B-Model, NoC, Zero-load predictive model
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Computer Science
Identifiers
urn:nbn:se:kth:diva-179688 (URN)10.1016/j.micpro.2015.09.002 (DOI)000366879500004 ()2-s2.0-84943171466 (Scopus ID)
Note

QC 20151221. QC 20160121

Available from: 2015-12-21 Created: 2015-12-21 Last updated: 2017-12-01Bibliographically approved
2. A scalable multi-dimensional NoC simulation model for diverse spatio-temporal traffic patterns
Open this publication in new window or tab >>A scalable multi-dimensional NoC simulation model for diverse spatio-temporal traffic patterns
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2013 (English)In: 2013 IEEE International 3D Systems Integration Conference, 3DIC 2013, IEEE , 2013, 6702365- p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper describes a powerful simulation platform that enables accurate simulations of numerous network configurations under realistic traffic patterns to predict the performance and power needs of a 3-D integrated system early in the design flow. The simulation platform can model virtually any sized 2-D or 3-D network configuration, providing low-cost and fast tradeoff evaluations of various systems architectures. The network simulator uses scalable RTL-level models that can be used for accurate power and timing analyses. We demonstrate the capability of our simulation model by analyzing the performance of various network topologies under spatio-temporal traffic patterns to show how the network topology can be adjusted to meet the performance requirements of a design before it is manufactured. The simulation results can be used to optimize the placement of cores and communication buses early in the flow. By using the model, standard applications such as mobile application processor, femto-cell base-stations on-chip and wide-IO TSV memory stacking can be simulated.

Place, publisher, year, edition, pages
IEEE, 2013
Series
IEEE International 3D Systems Integration Conference, ISSN 2164-0157
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-143176 (URN)10.1109/3DIC.2013.6702365 (DOI)000333258200052 ()2-s2.0-84893929548 (Scopus ID)978-146736484-3 (ISBN)
Conference
2013 IEEE International 3D Systems Integration Conference, 3DIC 2013; San Francisco, CA; United States; 2 October 2013 through 4 October 2013
Note

QC 20140317

Available from: 2014-03-17 Created: 2014-03-17 Last updated: 2015-12-21Bibliographically approved
3. Design Space Exploration of Clock-pumping Techniques to Reduce Through-Silicon-Via (TSV) Manufacturing Cost In 3-D Integration
Open this publication in new window or tab >>Design Space Exploration of Clock-pumping Techniques to Reduce Through-Silicon-Via (TSV) Manufacturing Cost In 3-D Integration
2012 (English)In: Proceedings of the 2012 IEEE 14th Electronics Packaging Technology Conference, EPTC 2012, IEEE , 2012, 19-22 p.Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, we explore the cost of clock pumping techniques implemented for scalable 3-D Integrated Systems in the complexity of interconnect, circuit, and architecture level changes. Their effect in terms of area and power for comparable performance is estimated. Our results show that by using 50% of the number of TSVs, we achieve the same performance as standard implementation with insignificant area and power overhead from the overall system cost. The proposed pumping technique can be used as one of the components in 3-D systems design for several applications that require logic-on-logic or memory-on-logic stacking.

Place, publisher, year, edition, pages
IEEE, 2012
Keyword
3D networks, Communication architectures, Communication schemes, Communication topologies, Cycle accurate, Design constraints, Design guidelines, Global interconnect delay, Integrated electronics, Network on chip, Technology solutions, Through silicon vias, Traffic pattern, Biological materials, Electric network topology, Interconnection networks, Microprocessor chips, Network performance, Routers, Scalability, Systems engineering, Three dimensional
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-122297 (URN)10.1109/EPTC.2012.6507043 (DOI)000320276500005 ()2-s2.0-84879751133 (Scopus ID)978-1-4673-4553-8 (ISBN)
Conference
2012 IEEE 14th Electronics Packaging Technology Conference, EPTC 2012; Singapore; Singapore; 5 December 2012 through 7 December 2012
Note

QC 20130528

Available from: 2013-05-17 Created: 2013-05-17 Last updated: 2015-12-21Bibliographically approved
4. Optimal Network Architectures for Minimizing Average Distance in k-ary n-dimensional Mesh Networks
Open this publication in new window or tab >>Optimal Network Architectures for Minimizing Average Distance in k-ary n-dimensional Mesh Networks
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2011 (English)In: NOCS 2011: The 5th ACM/IEEE International Symposium on Networks-on-Chip, ACM Digital Library, 2011, 57-64 p.Conference paper, Published paper (Refereed)
Abstract [en]

A general expression for the average distance for meshes of any dimension and radix, including unequal radices in different dimensions, valid for any traffic pattern under zero-load condition is formulated rigorously to allow its calculation without network-level simulations. The average distance expression is solved analytically for uniform random traffic and for a set of local random traffic patterns. Hot spot traffic patterns are also considered and the formula is empirically validated by cycle true simulations for uniform random, local, and hot spot traffic. Moreover, a methodology to attain closed-form solutions for other traffic patterns is detailed. Furthermore, the model is applied to guide design decisions. Specifically, we show that the model can predict the optimal 3-D topology for uniform and local traffic patterns. It can also predict the optimal placement of hot spots in the network. The fidelity of the approach in suggesting the correct design choices even for loaded and congested networks is surprising. For those cases we studied empirically it is 100%.

Place, publisher, year, edition, pages
ACM Digital Library, 2011
Keyword
Average Distance, Closed form solutions, Congested networks, Design decisions, General expression, Hot spot, Hot-spot traffic, Mesh network, Network-level simulations, Optimal network architecture, Optimal placements, Traffic pattern, Network architecture, Optimization, Three dimensional, Topology
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-63658 (URN)10.1145/1999946.1999956 (DOI)2-s2.0-79960296146 (Scopus ID)
Conference
5th ACM/IEEE International Symposium on Networks-on-Chip, NOCS 2011; Pittsburgh, PA; 1 May 2011 through 4 May 2011; Code 85530
Note

Key: Nostrum. QC 20120125. QC 20160209

Available from: 2012-01-24 Created: 2012-01-24 Last updated: 2016-02-09Bibliographically approved
5. 3-D Memory Organization and Performance Analysis for Multi-processor Network-On-Chip Architecture
Open this publication in new window or tab >>3-D Memory Organization and Performance Analysis for Multi-processor Network-On-Chip Architecture
2009 (English)In: 2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION, NEW YORK: IEEE , 2009, 42-48 p.Conference paper, Published paper (Refereed)
Abstract [en]

Several forms of processor memory organizations have been in use to optimally access off-chip memory systems mainly the Hard disk drives (HDD). Recent trends show that the solid state drives - (SSD) such as flash memories replacing HDDs and multi-processor memory system realized in a single 3-D structure with network-on-chip (NOC) architecture as a communication medium. This paper discusses high level memory organization and architectural modeling and simulation based on 3-D NOC. A comparative analysis among several models including Dance-hall, Sandwich, Terminal, Per-layer and mixed architectures is done. Simulations in cycle accurate 3-D NOC VHDL model are done to evaluate the performance each architecture in uniform and local traffic patterns.

Place, publisher, year, edition, pages
NEW YORK: IEEE, 2009
National Category
Computer and Information Science
Identifiers
urn:nbn:se:kth:diva-30156 (URN)10.1109/3DIC.2009.5306593 (DOI)000275055600008 ()2-s2.0-70549091100 (Scopus ID)978-1-4244-4511-0 (ISBN)
Conference
IEEE International Conference on 3D Systems Integration San Francisco, CA, SEP 28-30, 2009
Note
QC 20110303Available from: 2011-03-04 Created: 2011-02-21 Last updated: 2015-12-21Bibliographically approved
6. Scalability of Network-on-Chip Communication Architecture for 3-D Meshes
Open this publication in new window or tab >>Scalability of Network-on-Chip Communication Architecture for 3-D Meshes
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2009 (English)In: 2009 3RD ACM/IEEE INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP, NEW YORK: IEEE , 2009, 114-123 p.Conference paper, Published paper (Refereed)
Abstract [en]

Design Constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3-D chip stacks an enticing technology solution for massively integrated electronic systems. The scarcity of vertical interconnects however imposes special constraints on the design of the communication architecture. This article examines the performance and scalability of different communication topologiesfor 3-D Network-on-Chips (NoC) using Through-Silicon-Was (TSV) for inter-die connectivity. Cycle accurate RTL-level simulations are conducted for two communication schemes based on a 7-port switch and a centrally arbitrated vertical bus using different traffic patterns. The scalability of the 3-D NoC is examined under both communication architectures and compared to 2-D NoC structures in terms of throughput and latency in order to quantify the variation of network performance with the number of nodes and derive key design guidelines.

Place, publisher, year, edition, pages
NEW YORK: IEEE, 2009
Keyword
3D networks, Communication architectures, Communication schemes, Communication topologies, Cycle accurate, Design constraints, Design guidelines, Global interconnect delay, Integrated electronics, Network on chip, Technology solutions, Through silicon vias, Traffic pattern, Biological materials, Electric network topology, Interconnection networks, Microprocessor chips, Network performance, Routers, Scalability, Systems engineering, Three dimensional
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-30398 (URN)10.1109/NOCS.2009.5071459 (DOI)000271940100020 ()2-s2.0-70349808489 (Scopus ID)978-1-4244-4142-6 (ISBN)
Conference
3rd International Symposium on Networks-on-Chip, La Jolla, CA, MAY 10-13, 2009
Note
QC 20110301Available from: 2011-03-01 Created: 2011-02-24 Last updated: 2015-12-21Bibliographically approved
7. Bandwidth Optimization for Through Silicon Via(TSV) bundles in 3D Integrated Circuits
Open this publication in new window or tab >>Bandwidth Optimization for Through Silicon Via(TSV) bundles in 3D Integrated Circuits
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2009 (English)In: DATE'09 Friday Workshops - 3D Integration - Technology, Architecture, Design, Automation, and Test, Nice, France: DATE Conference , 2009, 283-287 p.Conference paper, Published paper (Refereed)
Abstract [en]

Through silicon vias (TSVs) are the backbone of 3D integration technology connecting vertically stacked ICs. Parallel TSVs in the form of bundles are used for vertical signaling.In this paper, we present the ways of maximizing the total bandwidth of a TSV bundle placed in a fixed area by varying the density and the geometries. The ways of optimizing the total bandwidth using analytical methods fora bundle of TSVs placed in a structure with a fixed area and length are examined. The result shows that for uniformly distributed TSVs, maximum bandwidth by proportionalplacement of fewer number of TSV in the bundle can be achieved.

Place, publisher, year, edition, pages
Nice, France: DATE Conference, 2009
Keyword
TSV bandwidth, 3D integration, TSV RC model
National Category
Embedded Systems
Identifiers
urn:nbn:se:kth:diva-62183 (URN)
Conference
DATE'09 Friday Workshops - 3D Integration - Technology, Architecture, Design, Automation, and Test. Nice, France. April 24, 2009
Projects
EU-FP7 ELITE-215030
Note

QC 20120119. QC 20160209

Available from: 2012-01-18 Created: 2012-01-18 Last updated: 2016-02-09Bibliographically approved
8. Automated Power and Latency Management in Heterogeneous 3D NoCs
Open this publication in new window or tab >>Automated Power and Latency Management in Heterogeneous 3D NoCs
2015 (English)Conference paper, Published paper (Refereed)
Abstract [en]

Beside different core sizes in many-core Systems-on-Chip, the costand reliability issues of TSVs move 3D NoCs toward heterogonousdesigns. Such heterogeneity introduces design complexity and newchallenges for obtaining a high performance, low power, low area,and a reliable design. By taking all these factors into account, wepropose a design as a combination of Q-Learning and deflectionrouting in a heterogeneous 3D NoCs. This design enables therouting algorithm to dynamically adjust itself to the underlyingtraffic condition and topology arrangement at run time. Thereby,the network can reach its optimal performance and minimum powerconsumption shortly after a reconfiguration either because of anoccurred fault in the network or a traffic change.

Place, publisher, year, edition, pages
Association for Computing Machinery (ACM), 2015
Keyword
q-routing, deflection routing, q-learning, irregular NoC
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-179689 (URN)10.1145/2835512.2835517 (DOI)2-s2.0-84959292826 (Scopus ID)978-1-4503-3963-6/15/12 (ISBN)
Conference
Eighth International Workshop on Network on Chip Architectures (NoCArc), 5 December 2015
Note

QC 20160226

Available from: 2015-12-21 Created: 2015-12-21 Last updated: 2016-04-13Bibliographically approved

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  • apa
  • harvard1
  • ieee
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