Synthesizing Code for GPGPUs from abstract formal models
2016 (English)In: 16th Conference on Languages, Design Methods, and Tools for Electronic System Design, FDL 2014, Springer, 2016, 115-134 p.Conference paper (Refereed)Text
Today multiple frameworks exist for elevating the task of writing programs for GPGPUs, which are massively data-parallel execution platforms. These are needed as writing correct and high-performing applications for GPGPUs is notoriously difficult due to the intricacies of the underlying architecture. However, the existing frameworks lack a formal foundation that makes them difficult to use together with formal verification, testing, and design space exploration. We present in this chapter a novel software synthesis tool—called f2cc—which is capable of generating efficient GPGPU code from abstract formal models based on the synchronous model of computation. These models can be built using high-level modeling methodologies that hide low-level architecture details from the developer. The correctness of the tool has been experimentally validated on models derived from two applications. The experiments also demonstrate that the synthesized GPGPU code yielded a 28× speedup when executed on a graphics card with 96 cores and compared against a sequential version that uses only the CPU.
Place, publisher, year, edition, pages
Springer, 2016. 115-134 p.
Architectural design, Codes (symbols), Computational linguistics, Program processors, Systems analysis, Design space exploration, Formal foundation, Graphics card, High-level modeling, High-performing applications, Software synthesis, Synchronous models, Writing projects, Design
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-181119DOI: 10.1007/978-3-319-24457-0_7ScopusID: 2-s2.0-84952775263ISBN: 9783319244556OAI: oai:DiVA.org:kth-181119DiVA: diva2:901799
14 October 2014 through 16 October 2014
QC 201602092016-02-092016-01-292016-02-09Bibliographically approved