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CuPAN - high throughput on-chip interconnection for neural networks
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2015 (English)In: 22nd International Conference on Neural Information Processing, ICONIP 2015, Springer, 2015, 559-566 p.Conference paper (Refereed)Text
Abstract [en]

In this paper, we present a Custom Parallel Architecture for Neural networks (CuPAN). CuPAN consists of streamlined nodes that each node is able to integrate a single or a group of neurons. It relies on a high-throughput and low-cost Clos on-chip interconnection network in order to efficiently handle inter-neuron communication. We show that the similarity between the traffic pattern of neural networks (multicast-based multi-stage traffic) and topological characteristics of multi-stage interconnection networks (MINs) makes neural networks naturally suited to the MINs. The Clos network, as one of the most important classes of MINs, provide scalable low-cost interconnection fabric composed of several stages of switches to connect two groups of nodes and interestingly, can support multicast in an efficient manner. Our evaluation results show that CuPAN can manage the multicast-based traffic of neural networks better than the mesh-based topologies used in many parallel neural network implementations and gives lower average message latency, which directly translates to faster neural processing.

Place, publisher, year, edition, pages
Springer, 2015. 559-566 p.
Lecture Notes in Computer Science, ISSN 0302-9743 ; 9491
Keyword [en]
Clos network, Multicast, Network-on-chip, Neural networks, Information science, MESH networking, Multicasting, Parallel architectures, Program processors, Switching networks, Throughput, Topology, VLSI circuits, Clos networks, Evaluation results, Interconnection fabrics, Multistage interconnection network, On-chip interconnection, On-chip interconnection network, Parallel neural networks, Topological characteristics, Integrated circuit interconnects
National Category
Communication Systems
URN: urn:nbn:se:kth:diva-181525DOI: 10.1007/978-3-319-26555-1_63ISI: 000371579800063ScopusID: 2-s2.0-84952009318ISBN: 9783319265544OAI: diva2:911315
9 November 2015 through 12 November 2015

QC 20160311

Available from: 2016-03-11 Created: 2016-02-02 Last updated: 2016-04-01Bibliographically approved

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Daneshtalab, Masoud
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Electronics and Embedded Systems
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