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On Constructing Secure and Hardware-Efficient Invertible Mappings
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.ORCID iD: 0000-0001-7382-9408
2016 (English)In: Proceedings of IEEE International Symposium on Multiple-Valued Logic, 2016Conference paper (Refereed)
Abstract [en]

Our society becomes increasingly dependent on wireless communications. The tremendous growth in the number and type of wirelessly connected devices in a combination with the dropping cost for performing cyberattacks create new challenges for assuring security of services and applications provided by the next generation of wireless communication networks. The situation is complicated even further by the fact that many end-point Internet of Things (IoT) devices have very limited resources for implementing security functionality. This paper addresses one of the aspects of this important, many-faceted problem - the design of hardware-efficient cryptographic primitives suitable for the protection of resource-constrained IoT devices. We focus on cryptographic primitives based on the invertible mappings of type {0,1,…,2n−1}→{0,1,…,2n−1}. In order to check if a given mapping is invertible or not, we generally need an exponential in n number of steps. In this paper, we derive a sufficient condition for invertibility which can be checked in O(n2N) time, where N is the size of representation of the largest function in the mapping. Our results can be used for constructing cryptographically secure invertible mappings which can be efficiently implemented in hardware.

Place, publisher, year, edition, pages
Keyword [en]
invertible mapping, cryptographic primitive, security
National Category
Engineering and Technology
URN: urn:nbn:se:kth:diva-183978OAI: diva2:913286
IEEE International Symposium on Multiple-Valued Logic
Swedish Foundation for Strategic Research , SM14-0016

NV 20160405

Available from: 2016-03-21 Created: 2016-03-21 Last updated: 2016-04-05Bibliographically approved

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Dubrova, Elena
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