Area- and Efficiency-Optimized Junction Termination for a 5.6 kV SiC BJT Process with Low ON-Resistance
2015 (English)In: 2015 IEEE 27TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & IC'S (ISPSD), IEEE , 2015, 249-252 p.Conference paper (Refereed)Text
Implantation-free mesa-etched 4H-SiC bipolar junction transistors (BJTs) with a near-ideal breakdown voltage of 5.6 kV (about 92% of the theoretical value) are fabricated, measured and analyzed by device simulation. An efficient and optimized termination; area-optimized three-zone junction termination extension (O-JTE) is implemented, reducing the total area (and substrate cost) by about 30% compared to the traditional JTE designs. A maximum current gain of beta = 44 at a current density of 472 A/cm(2), and a specific on-resistance of R-ON = 18.8 m Omega.cm(2) is obtained for the device. The device shows a negative temperature coefficient of the current gain (beta = 14.5 at 200 degrees C) and a positive temperature coefficient of on-resistance (R-ON = 57.3 m Omega.cm(2) at 200 degrees C).
Place, publisher, year, edition, pages
IEEE , 2015. 249-252 p.
, Proceedings of the International Symposium on Power Semiconductor Devices & ICs, ISSN 1063-6854
4H-SiC BJT, implantation-free, area-optimized junction termination extension (O-JTE), current gain, on-resistance
IdentifiersURN: urn:nbn:se:kth:diva-184071DOI: 10.1109/ISPSD.2015.7123436ISI: 000370717300061ScopusID: 2-s2.0-84944681235ISBN: 978-1-4799-6261-7OAI: oai:DiVA.org:kth-184071DiVA: diva2:914031
27th International Symposium on Power Semiconductor Devices and ICs (ISPSD), MAY 10-14, 2015, Hong Kong, PEOPLES R CHINA
QC 201603232016-03-232016-03-222016-03-23Bibliographically approved