Change search
ReferencesLink to record
Permanent link

Direct link
Non-Blocking Testing for Network-on-Chip
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.ORCID iD: 0000-0001-6289-1521
Show others and affiliations
2016 (English)In: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 65, no 3, 679-692 p.Article in journal (Refereed) PublishedText
Abstract [en]

To achieve high reliability in on-chip networks, it is necessary to test the network as frequently as possible to detect physical failures before they lead to system-level failures. A main obstacle is that the circuit under test has to be isolated, resulting in network cuts and packet blockage which limit the testing frequency. To address this issue, we propose a comprehensive network-level approach which could test multiple routers simultaneously at high speed without blocking or dropping packets. We first introduce a reconfigurable router architecture allowing the cores to keep their connections with the network while the routers are under test. A deadlock-free and highly adaptive routing algorithm is proposed to support reconfigurations for testing. In addition, a testing sequence is defined to allow testing multiple routers to avoid dropping of packets. A procedure is proposed to control the behavior of the affected packets during the transition of a router from the normal to the testing mode and vice versa. This approach neither interrupts the execution of applications nor has a significant impact on the execution time. Experiments with the PARSEC benchmarks on an 8x8 NoC-based chip multiprocessors show only 3 percent execution time increase with four routers simultaneously under test.

Place, publisher, year, edition, pages
IEEE , 2016. Vol. 65, no 3, 679-692 p.
Keyword [en]
Reconfigurable router architecture, built-in self-test, on-chip interconnect, single-chip multiprocessors
National Category
Computer Science
Identifiers
URN: urn:nbn:se:kth:diva-184024DOI: 10.1109/TC.2015.2489216ISI: 000370729600002ScopusID: 2-s2.0-84962127823OAI: oai:DiVA.org:kth-184024DiVA: diva2:914489
Note

QC 20160324

Available from: 2016-03-24 Created: 2016-03-22 Last updated: 2016-04-13Bibliographically approved

Open Access in DiVA

No full text

Other links

Publisher's full textScopus

Search in DiVA

By author/editor
Ebrahimi, MasoumehDaneshtalab, Masoud
By organisation
Industrial and Medical ElectronicsElectronics and Embedded Systems
In the same journal
I.E.E.E. transactions on computers (Print)
Computer Science

Search outside of DiVA

GoogleGoogle Scholar
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

Altmetric score

Total: 25 hits
ReferencesLink to record
Permanent link

Direct link