Non-Blocking Testing for Network-on-Chip
2016 (English)In: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 65, no 3, 679-692 p.Article in journal (Refereed) PublishedText
To achieve high reliability in on-chip networks, it is necessary to test the network as frequently as possible to detect physical failures before they lead to system-level failures. A main obstacle is that the circuit under test has to be isolated, resulting in network cuts and packet blockage which limit the testing frequency. To address this issue, we propose a comprehensive network-level approach which could test multiple routers simultaneously at high speed without blocking or dropping packets. We first introduce a reconfigurable router architecture allowing the cores to keep their connections with the network while the routers are under test. A deadlock-free and highly adaptive routing algorithm is proposed to support reconfigurations for testing. In addition, a testing sequence is defined to allow testing multiple routers to avoid dropping of packets. A procedure is proposed to control the behavior of the affected packets during the transition of a router from the normal to the testing mode and vice versa. This approach neither interrupts the execution of applications nor has a significant impact on the execution time. Experiments with the PARSEC benchmarks on an 8x8 NoC-based chip multiprocessors show only 3 percent execution time increase with four routers simultaneously under test.
Place, publisher, year, edition, pages
IEEE , 2016. Vol. 65, no 3, 679-692 p.
Reconfigurable router architecture, built-in self-test, on-chip interconnect, single-chip multiprocessors
IdentifiersURN: urn:nbn:se:kth:diva-184024DOI: 10.1109/TC.2015.2489216ISI: 000370729600002ScopusID: 2-s2.0-84962127823OAI: oai:DiVA.org:kth-184024DiVA: diva2:914489
QC 201603242016-03-242016-03-222016-04-13Bibliographically approved