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A Comparative Design Study of Continuous-Time Incremental Sigma-Delta ADC Architectures
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0002-4691-2318
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0003-3802-7834
2016 (English)In: International journal of circuit theory and applications, ISSN 0098-9886, E-ISSN 1097-007X, Vol. 44, no 12, 2147-2163 p.Article in journal (Refereed) Published
Abstract [en]

This paper presents a comparative design study of continuous-time (CT) incremental sigma-delta (IΣΔ) ADCs, which can expand another dimension of the IΣΔ ADC world that is dominated by discrete-time implementations. Several CT IΣΔ ADC architectures are introduced and analyzed aiming to reduce the modulator’s sampling frequency and consequently the power dissipation. Based on the analytical results, three CT IΣΔ ADCs are selected to be examined, implemented, and tested. The three ADC prototypes, fabricated in a standard 0.18 μm CMOS technology, demonstrate competitive figure-of-merits in terms of power efficiency compared to the state-of-the-art counterparts.

Place, publisher, year, edition, pages
John Wiley & Sons, 2016. Vol. 44, no 12, 2147-2163 p.
Keyword [en]
A/D conversion; incremental sigma-delta; continuous-time; extended-range; two-step
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-185162ISI: 000389841700008Scopus ID: 2-s2.0-84971012114OAI: oai:DiVA.org:kth-185162DiVA: diva2:918782
Funder
Swedish Research Council
Note

QC 20160512

Available from: 2016-04-11 Created: 2016-04-11 Last updated: 2017-01-11Bibliographically approved

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